91
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Switching characteristics (VCC = 5 V±10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz when the clock source select bit = “0”,
unless otherwise noted)
Memory expansion and Microprocessor mode : Low-speed running
Symbol
Parameter
Unit
tw(
φH), tw(φL)
td(
φ1–WR)
td(
φ1–RD)
tw(WR)
tw(RD)
td(A–WR)
td(A–RD)
td(A–ALE)
td(BHE–WR)
td(BHE–RD)
td(BHE–ALE)
td(CS–WR)
td(CS–RD)
td(CS–ALE)
td(WR–DLQ/DHQ)
tpxz(WR–DLZ/DHZ)
td(ALE–WR)
td(ALE–RD)
tw(ALE)
th(WR–A)
th(RD–A)
th(WR–BHE)
th(RD–BHE)
th(WR–CS)
th(RD–CS)
th(WR–DLQ/DHQ)
tpzx(WR–DLZ/DHZ)
td(LA–WR)
td(LA–RD)
td(LA–ALE)
th(ALE–LA)
tpxz(RD–DLZ)
tpzx(RD–DLZ)
td(WR–PiQ)
φ high-level pulse width, φ low-level pulse width (Note)
WR output delay time
RD output delay time
WR low-level pulse width (Note)
RD low-level pulse width (Note)
Address output delay time (Note)
BHE output delay time (Note)
__
___
__
___
____
BHE output delay time (Note)
Chip select output delay time (Note)
Data output delay time
Floating start delay time (Note)
ALE output delay time
ALE pulse width (Note)
Address hold time (Note)
BHE hold time (Note)
Chip select hold time (Note)
Data hold time (Note)
Floating release delay time
Address output delay time (Note)
Address hold time
Floating start delay time
Floating release delay time (Note)
Port Pi data output delay time (i = 4—9, 11)
Min.
20
–7
60
15
8
15
8
15
8
4
22
10
15
0
12
5
9
18
2-
φ access
Max.
12
35
30
5
60
3-
φ access
Min.
20
–7
140
15
8
15
8
15
8
4
22
10
15
0
12
5
9
18
Max.
12
35
30
5
60
Min.
20
–7
140
95
55
95
55
95
55
4
62
10
15
0
92
52
25 (Note)
18
4-
φ access
Max.
12
35
30
5
60
ns
: f(XIN) = 12.5 MHz when the clock source selet bit = “1”
Note: Since the values depend on external clock input frequency f(XIN), calculate them using the bus timing data formula on the next page.