參數(shù)資料
型號： M37754S4CGP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁數(shù)： 31/114頁
文件大小： 1116K
代理商： M37754S4CGP
23
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
TIMER
There are eight 16-bit timers. They are divided by type into timer A(5)
and timer B(3).
The timer I/O pins are multiplexed with I/O pins for port P5 and P6.
To use these pins as timer input pins, the data direction register bit
corresponding to the pin must be cleared to “0” to specify input mode.
TIMER A
Figure 17 shows a block diagram of timer A.
Timer A has four modes: timer mode, event counter mode, one-shot
pulse mode, and pulse width modulation mode. The mode is se-
lected with bits 0 and 1 of the timer Ai mode register (i = 0 to 4). Each
of these modes is described below.
(1) Timer mode [00]
Figure 18 shows the bit configuration of the timer Ai mode register
during timer mode. Bits 0 and 1 of the timer Ai mode register must be
“0” in timer mode. Bits 3, 4, and 5 are used to select the gate func-
tion. Bits 4 and 5 must be “0” when not selecting the gate function.
Bit 3 is ignored if bit 4 is “0”.
Bits 6 and 7 are used to select the timer counter source.
The counting of the selected clock starts when the count start bit is
“1” and stops when it is “0”.
Figure 19 shows the bit configuration of the count start bit. The
counter is decremented, an interrupt is caused and the interrupt re-
quest bit in the timer Ai interrupt control register is set when the con-
tents becomes 000016. At the same time, the contents of the reload
register is transferred to the counter and count is continued.
When data is written to timer Ai register with timer Ai halted, the same
data is also written to the reload register and the counter. When data
is written to timer Ai which is busy, the data is written to the reload
register, but not to the counter. The new data is reloaded from the re-
load register to the counter at the next reload time and counting con-
tinues. The contents of the counter can be read at any time.
When the value set in the timer Ai register is n, the timer frequency
dividing ratio is 1/(n+1).
Fig. 17 Block diagram of timer A
Timer
One-shot
Pulse width modulation
Count start bit
(4016)
Down count
Data bus (odd)
Data bus (even)
Reload register(16)
Counter(16)
(Lower 8 bits)
(Higher 8 bits)
Always decremented
except in event count mode
Timer A0 4716 4616
Timer A1 4916 4816
Timer A2 4B16 4A16
Timer A3 4D16 4C16
Timer A4 4F16 4E16
Up/Down
Toggle flip-flop
Up-down bit
(4416)
Polarity
selection
Addresses
External trigger
Event counter
TAiIN
(i = 0–4)
TAiOUT
(i = 0–4)
Timer(gate function)
Clock source selection
Pulse output
Pf2
Pf16
Pf64
Pf512
Note: Perform write and read to/from timer Ai register in the condition of 16-bit data length : data length flag (m) = “0”.
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相關代理商/技術參數(shù)
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