參數(shù)資料
型號： M37754S4CGP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁數(shù)： 68/114頁
文件大?。?/td> 1116K
代理商： M37754S4CGP
57
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 69 shows the comparator function select register (address
6416) bit configuration. Bits 7 to 0 correspond to channels 7 to 0 re-
spectively. Each channel can be selected as either an A-D converter
or a comparator. When the bit is “0”, the channel corresponding to it
functions as a 10-bit or an 8-bit A-D converter. When the bit is “1”, the
channel functions as a comparator.
When selecting an A-D converter, an input voltage to a selected ana-
log input pin is A-D converted and the result is stored into the A-D
register.
When selecting a comparator, D-A conversion is performed to the
value of which high-order 8 bits are the value stored in an even ad-
dress of the A-D converter and of which low-order 2 bits are “102.”
Then, this D-A converted value is compared with the voltage sup-
plied to an analog input pin. After the comparison, when the voltage
supplied to an analog input pin is higher, “1” is stored into the com-
parator result register (address 6616) shown in Figure 70. When it is
lower, “0” is stored into that register.
Be sure to perform only read to the A-D register of which channel is
selected as an A-D converter, and perform only write to the A-D reg-
ister of which channel is selected as a comparator. Additionally, do
not write to the comparator function select register and the A-D reg-
ister while an A-D converter or a comparator is operating.
Port direction register’s bits corresponding to pins to be A-D con-
verted must be “0” (input mode) because analog input ports are mul-
tiplexed with port P7.
Figure 71 shows the bit configuration of the A-D control register 0
(address 1E16) and the A-D control register 1 (address 1F16).
An operation clock (
φAD) of an A-D converter or a comparator can be
selected with bit 7 of the A-D control register 0 and bit 4 of the A-D
control register 1.
When bit 4 (frequency select flag 1) of the A-D control register 1 is
“0”,
φAD becomes Pf8 when bit 7 (frequency select flag 0) of the A-D
control register 0 is “0”,
φAD becomes Pf4 when bit 7 of the A-D con-
trol register 0 is “1”.
When the frequency select flag 1 is “1”,
φAD becomes Pf2 when the
frequency select flag 0 is “0”,
φAD becomes φ1 when the frequency
select flag 0 is “1”. The last case is used when
φ1 is forcibly used as
φAD in high-speed running (f(XIN) > φ1 > 12.5 MHz). However, this se-
lection is available only in 8-bit resolution mode.
φAD during A-D conversion must be 250 kHz or more because the
comparator uses a capacity coupling amplifier.
Bit 3 of A-D control register 1 is used to select whether to regard the
conversion result as 10-bit or as 8-bit data. The conversion result is
regarded as 10-bit data when bit 3 is “1” and as 8-bit data when bit 3
is “0”.
When the conversion result is used as 10-bit data, the low-order 8
bits of the conversion result is stored in the even address of the cor-
responding A-D register and the high-order 2 bits are stored in bits 0
and 1 at the odd address of the corresponding A-D register. Bits 2 to
7 of the A-D register odd address are “0000002” when read.
When the conversion result is used as 8-bit data, the high-order 8
bits of the 10-bit A-D conversion result are stored in even address of
the corresponding A-D register. In this case, the value at the A-D
register’s odd address is “0016” when read.
Whether to connect the reference voltage input (VREF) with the lad-
Fig. 69 Comparator function select register bit configuration
Fig. 70 Comparator result register bit configuration
der network or not depends on bit 5 of the A-D control register 1. The
VREF pin is connected when bit 5 is “0” and is disconnected when bit
5 is “1” (High impedance state).
When A-D or D-A conversion is not performed, current from the VREF
pin to the ladder network can be cut off by disconnecting ladder net-
work from the VREF pin.
Before starting A-D or D-A conversion, wait for 1
s or more after
clearing bit 5 to “0”.
Note: Do not access with the SEB or CLB instruction.
76543210
Comparator function select register
“0” : Select A-D converter
“1” : Select comparator
AN0 pin comparator function select bit
AN1 pin comparator function select bit
AN2 pin comparator function select bit
AN3 pin comparator function select bit
AN4 pin comparator function select bit
AN5 pin comparator function select bit
AN6 pin comparator function select bit
AN7 pin comparator function select bit
Address
6416
76543210
Comparator result register
“0” : ANi input level is lower than set digital value
“1” : ANi input level is higher than set digital value
AN0 pin comparator result bit
AN1 pin comparator result bit
AN2 pin comparator result bit
AN3 pin comparator result bit
AN4 pin comparator result bit
AN5 pin comparator result bit
AN6 pin comparator result bit
AN7 pin comparator result bit
Address
6616
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