參數(shù)資料
型號(hào)： M37754S4CGP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁數(shù)： 65/114頁
文件大?。?/td> 1116K
代理商： M37754S4CGP
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
54
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
____
Once transmission has started, the TEi flag, TIi flag, and CTSi signal
____
(if CTSi input is selected ) are ignored until data transmission is com-
pleted.
Therefore, transmission does not stop until it completes event if the
TEi flag is cleared during transmission.
The transmission start condition indicated by TEi flag, TIi flag, and
____
CTSi is checked while the TENDi signal shown in Figure 65 is “H”.
Therefore, data can be transmitted continuously if the next transmis-
sion data is written in the transmit buffer register and TIi flag is
cleared to “0” before the TENDi signal goes “H”.
Bit 3 (TXEPTYi flag) of UARTi Transmit/Receive control register 0
changes to “1” at the next cycle just after the TENDi signal goes “H”
and changes to “0” when transmission starts. Therefore, this flag can
be used to determine whether data transmission is completed.
When the TIi flag changes from “0” to “1”, the interrupt request bit of
the UARTi transmit interrupt control register is set to “1”.
Transmission
Transmission is started when bit 0 (TEi flag) of UARTi Transmit/Re-
____
ceive control register 1 is “1”, bit 1 (TIi flag) is “0”, and CTSi input is
____
“L” if CTSi input is selected. As shown in Figures 65 and 66, data is
output from the TXDi pin with the stop bit or parity bit specified by bits
4 to 6 of UARTi Transmit/Receive mode register. The data is output
from the least significant bit.
The TIi flag indicates whether the transmit buffer is empty or not. It is
cleared to “0” when data is written in the transmit buffer, and is set to
“1” when the contents of the transmit buffer register is transferred to
the transmit register.
When the transmit register becomes empty after the contents has
been transmitted, data is transferred automatically from the transmit
buffer register to the transmit register if the next transmit start condi-
tion is satisfied.
Fig. 65 Transmit timing example when 8-bit asynchronous communication with parity and 1 stop bit selected
Fig. 66 Transmit timing example when 9-bit asynchronous communication with no parity and 2 stop bits selected
(1/Pfi or 1/fEXT)
× (n + 1) × 16
Written in transmit buffer register
Transmission clock
TEi
TIi
CTSi
TENDi
TXDi
TXEPTYi
D0 D1
ST
Start bit
Parity bit Stop bit
D2 D3 D4 D5 D6 D7
PSP ST D0 D1 D2 D3 D4 D5 D6 D7
PSP
ST D0 D1
Transmit register
← Transmit
buffer register
Stopped because TEi = “0”
(1/Pfi or 1/fEXT)
× (n + 1) × 16
Written in transmit buffer register
Transmission clock
TEi
TIi
TENDi
TXDi
TXEPTYi
D0 D1
ST
D2 D3 D4 D5 D6 D7 D8
SP
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
ST D0
D2
D1
Transmit register
← Transmit
buffer register
Stopped because TEi = “0”
Start bit
Stop bit
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