Rev.2.00
Aug 28, 2006
page 56 of 119
7643 Group
REJ03B0054-0200
FREQUENCY SYNTHESIZER (PLL)
The frequency synthesizer generates the 48 MHz clock required
by fUSB and fSYN, which are multiples of the external input refer-
ence f(XIN). Figure 51 shows the block diagram for the frequency
synthesizer circuit.
The Frequency Synthesizer Input Bit selects either f(XIN) or
f(XCIN) as an input clock fIN for the frequency synthesizer.
The Frequency Synthesizer Multiply Register 2 (FSM2: address
006E16) divides fIN to generate fPIN, where
fPIN = fIN / 2(n + 1), n: value set to FSM2.
When the value of Frequency Synthesizer Multiply Register 2 is
set to 255, the division is not performed and fPIN will equal fIN.
fVCO is generated according to the contents of Frequency Synthe-
sizer Multiply Register 1 (FSM1: address 006D16), where
fVCO = fPIN {2(n + 1)}, n: value set to FSM1.
Set the value of FSM1 so that the value of fVCO is 48 MHz.
fSYN is generated according to the contents of the Frequency Syn-
thesizer Divide Register (FSD: address 006F16), where
fSYN = fVCO / 2(m + 1), m: value set to FSD.
When the value of the Frequency Synthesizer Divide Register is
set to 255, the division is not performed and fSYN becomes invalid.
[Frequency Synthesizer Control Register] FSC
Setting the Frequency Synthesizer Enable Bit (FSE) to “1” enables
the frequency synthesizer. When the Frequency Synthesizer Lock
Status Bit (LS) is “1” in the frequency synthesizer enabled, this in-
dicates that fSYN and fVCO have correct frequencies.
sNotes
Make sure to connect a low-pulse filter to the LPF pin when using
the frequency synthesizer. In addition, please refer to “Program-
ming Notes: Frequency Synthesizer” when recovering from a
Hardware Reset.
FSM2
Data Bus
FSM1
FSC
Prescaler
fIN
fPIN
fVCO
fSYN
fUSB
(address 006E16)
(address 006D16)
(address 006C16)
(address 006F16)
FSD
Frequency
Multiplier
Frequency Divider
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Fig. 51 Frequency synthesizer block diagram