參數(shù)資料
型號: M37643M8-XXXHP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP80
封裝: 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數(shù): 104/123頁
文件大?。?/td> 1292K
代理商: M37643M8-XXXHP
Rev.2.00
Aug 28, 2006
page 79 of 119
7643 Group
REJ03B0054-0200
Reset input “L” pulse width
Main clock input cycle time (Note)
Main clock input “H” pulse width
Main clock input “L” pulse width
Sub-clock input cycle time
Sub-clock input “H” pulse width
Sub-clock input “L” pulse width
INT0, INT1 input cycle time
INT0, INT1 input “H” pulse width
INT0, INT1 input “L” pulse width
Timer TOUT delay time
Serial I/O external clock input cycle time
Serial I/O external clock input “H” pulse width
Serial I/O external clock input “L” pulse width
Serial I/O input setup time (external clock)
Serial I/O input hold time (external clock)
Serial I/O output delay time (external clock)
Serial I/O SRDY valid time (external clock)
Serial I/O internal clock output cycle time
Serial I/O internal clock output “H” pulse width
Serial I/O internal clock output “L” pulse width
Serial I/O input setup time (internal clock)
Serial I/O input hold time (internal clock)
Serial I/O output delay time (internal clock)
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(XCIN)
tWH(XCIN)
tWL(XCIN)
tC(INT)
tWH(INT)
tWL(INT)
td(
φ -TOUT)
tC(SCLKE)
tWH(SCLKE)
tWL(SCLKE)
tsu(SRXD-SCLKE)
th(SCLKE-SRXD)
td(SCLKE-STXD)
tv(SCLKE-SRDY)
tc(SCLKI)
tWH(SCLKI)
tWL(SCLKI)
tsu(SRXD-SCLKI)
th(SCLKI-SRXD)
td(SCLKI-STXD)
Limits
s
ns
Parameter
Min.
2
41.66
0.4tc(XIN)
200
0.4tc(XCIN)
250
110
450
220
190
20
15
300
0.5tc(SCLKI) – 5
20
5
Typ.
Max.
Symbol
Unit
Table 18 Timing requirements (Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted)
Note: Make sure not to exceed 6 MHz of
φ, in other words, tc(φ) ≥ 166.66 ns).
Timing Requirements
In Vcc = 3 V
17
34
35
5
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