- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄69014 > M37643M8-XXXHP 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP80 PDF資料下載
參數(shù)資料
| 型號： | M37643M8-XXXHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 64/123頁 |
| 文件大?。?/td> | 1292K |
| 代理商： | M37643M8-XXXHP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁當(dāng)前第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁
Rev.2.00
Aug 28, 2006
page 43 of 119
7643 Group
REJ03B0054-0200
USB Reception
Endpoint 0 to Endpoint 2 have OUT (receive) FIFOs individually.
Each endpoint’s FIFO is configured in following way:
Endpoint 0: 16-byte
Endpoint 1: 128-byte
Endpoint 2: Mode 0: 32-byte
Mode 1: 128-byte
When Endpoint 2 is used for data receive, the OUT FIFO size can
be selected. Endpoint 2 have 2 modes programmable IN-FIFO.
Each mode can be selected by the USB endpoint FIFO mode se-
lection register (address 005F16).
Data transmitted from the host-PC is stored in Endpoint x FIFO
(006016 to 006216). Every time the data is stored in the FIFO, the
internal OUT FIFO write pointer is increased by 1. When one com-
plete data packet is stored, the OUT_PKT_RDY flag is set to “1”
and the number of received data packets is stored in USB End-
point x OUT write count register. When the AUTO_CLR bit is “1”
and the received data is read out from the OUT FIFO, the
OUT_PKT_RDY flag is cleared to “0”. When the AUTO_CLR bit is
“1”, the OUT_PKT_RDY flag will not be cleared automatically by
the FIFO read; it must be cleared by software. (The AUTO-CLR bit
function is not applicable in Endpoint 0.)
When MAXP size
≤ (a half of OUT FIFO size), the OUT_FIFO can
receive 2 packets (double buffer). At this time, the OUT_ FIFO sta-
tus can be checked by the OUT_PKT_RDY flag. When the FIFO
holds two packets and one packet is read from the FIFO, the
OUT_PKT_RDY flag is not cleared even if it is set to “0”. (The flag
returns from “0” to “1” in one
φ cycle after the read-out). During
double buffer mode, the USB Endpoint x OUT write count register
holds the number of previously received packets. This count regis-
ter is updated after reading out one of packets in the OUT FIFO
and clearing the OUT_PKT_RDY flag to “0”.
TOGGLE Initialization
In order to initialize the data toggle sequence bit of the endpoint,
in other words, resetting the next data packet to DATA0; set the
TOGGLE_INT bit to “1” and then clear back to “0”.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M37643F8HP | 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQFP80 |
| M37700E2AFS | 16-BIT, UVPROM, 16 MHz, MICROCONTROLLER, CQCC80 |
| M37700E2AXXXFP | 16-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| M37701E2-XXXSP | 16-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PDIP64 |
| M37702E4EXXXFP | 16-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP80 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M3764A-12 | 制造商:OK International 功能描述: |
| M3765 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:HORN/SIREN WITH SOFT CHIRP 6 ALARM SOUNDS |
| M3766 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:HORN/SIREN WITH SOFT CHIRP 6 ALARM SOUNDS |
| M37702E2LGP | 制造商:Mitsubishi Electric 功能描述: |
| M37702E4BFS | 制造商:Renesas Electronics Corporation 功能描述:EPROM MCU/8BIT CMOS EMULATION CHIP - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。