參數(shù)資料
型號: M37643M8-XXXHP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP80
封裝: 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數(shù): 68/123頁
文件大?。?/td> 1292K
代理商: M37643M8-XXXHP
Rev.2.00
Aug 28, 2006
page 47 of 119
7643 Group
REJ03B0054-0200
[USB Interrupt Status Registers 1 and 2] USBIS1, USBIS2
The USB interrupt status registers are used to indicate the condi-
tion that caused a USB function interrupt to be generated. Each
status flag and bit can be cleared to “0” by writing “1” to the corre-
sponding bit. Make sure to write to/read from the USB interrupt
status register 1 first and then USB interrupt status register 2.
USB interrupt status register 1 (address 005216)
USBIS1
USB endpoint 0 interrupt status flag (INTST0)
0: Except the following conditions
1: Set at any one of the following conditions:
A packet data of endpoint 0 is successfully received
A packet data of endpoint 0 is successfully sent
DATA_END bit of endpoint 0 is cleared to “0”
FORCE_STALL bit of endpoint 0 is set to “1”
SETUP_END bit of endpoint 0 is set to “1”.
Reserved bit (“0” at read/write)
USB endpoint 1 IN interrupt status flag (INTST2)
0: Except the following condition
1: Set at which of the following condition:
A packet data of endpoint 1 is successfully sent
USB endpoint 1 OUT interrupt status flag (INTST3)
0: Except the following conditions
1: Set at any one of the following conditions:
A packet data of endpoint 1 is successfully received
FORCE_STALL bit of endpoint 1 is set to “1”.
USB endpoint 2 IN interrupt status flag (INTST4)
0: Except the following condition
1: Set at which of the following condition:
A packet data of endpoint 2 is successfully sent
USB endpoint 2 OUT interrupt status flag (INTST5)
0: Except the following conditions
1: Set at any one of the following conditions:
A packet data of endpoint 2 is successfully received
FORCE_STALL bit of endpoint 2 is set to “1”.
Reserved bit (“0” at read/write)
b0
b7
0
Fig. 38 Structure of USB interrupt status register 1
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