參數(shù)資料
型號(hào): M37643M8-XXXHP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP80
封裝: 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁(yè)數(shù): 42/123頁(yè)
文件大?。?/td> 1292K
代理商: M37643M8-XXXHP
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Rev.2.00
Aug 28, 2006
page 23 of 119
7643 Group
REJ03B0054-0200
Key Input Interrupt (Key-on Wake-Up)
A key input interrupt request is generated by applying “L” level to any
pin of port P2 that have been set to input mode. In other words, it is
generated when AND of input level goes from “1” to “0”. An example
of using a key input interrupt is shown in Figure 18, where an inter-
rupt request is generated by pressing one of the keys consisted as
an active-low key matrix which inputs to ports P20–P24.
Fig. 18 Connection example when using key input interrupt and port P2 block diagram
Port P27
latch
Port P27
direction register = “1”
P27 output
Port P2 pull-up control register
Bit 7 = “0”
Port PXx
“L” level output
Key input interrupt request
Falling edge
detector
P26 output
P25 output
P24 input
P23 input
P22 input
P21 input
P20 input
Port P26
latch
Port P26
direction register = “1”
Port P2 pull-up control register
Bit 6 = “0”
Falling edge
detector
Port P25
latch
Port P25
direction register = “1”
Port P2 pull-up control register
Bit 5 = “0”
Falling edge
detector
Port P24
latch
Port P24
direction register = “0”
Port P2 pull-up control register
Bit 4 = “0”
Falling edge
detector
Port P23
latch
Port P23
direction register = “0”
Port P2 pull-up control register
Bit 3 = “0”
Falling edge
detector
Port P22
latch
Port P22
direction register = “0”
Port P2 pull-up control register
Bit 2 = “0”
Falling edge
detector
Port P21
latch
Port P21
direction register = “0”
Port P2 pull-up control register
Bit 1 = “0”
Falling edge
detector
Port P20
latch
Port P2 pull-up control register
Bit 0 = “0”
Falling edge
detector
Port P20
direction register = “0”
Port P2
Input reading circuit
P-channel transistor for pull-up
CMOS output buffer
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