參數(shù)資料
型號(hào)： M34552G8HFP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP48
封裝： 7 X 10 MM, 0.65 MM PITCH, PLASTIC, QFP-48
文件頁數(shù)： 93/143頁
文件大小： 0K
代理商： M34552G8HFP
Rev.3.02
Dec 22, 2006
page 51 of 142
REJ03B0023-0302
4552 Group
VOLTAGE DROP DETECTION CIRCUIT
(only for H version)
The built-in voltage drop detection circuit is designed to detect a
drop in voltage and to reset the microcomputer if the supply voltage
drops below a set value.
Fig. 41 Voltage drop detection reset circuit
Fig. 42 Voltage drop detection circuit operation waveform
EPOF instruction +POF instruction
EPOF instruction +POF2 instruction
Q
S
R
SVDE instruction
Internal reset signal
Voltage drop detection circuit
Reset signal
–
VRST
Voltage drop detection circuit
Internal reset signal
T3F flag
Key-on wakeup signal
QS
R
+
VRST (reset release voltage)
+
-
VDD
Voltage drop detection circuit
Reset signal
Microcomputer starts operation after
on-chip oscillator (internal oscillator)
clock is counted 1376 times.
VRST (reset occurrence voltage)
RESET pin
Note: Detection voltage hysteresis of voltage drop detection circuit is 0.1 V (Typ).
(2) Note on voltage drop detection circuit
The voltage drop detection circuit detection voltage of this prod-
uct is set up lower than the minimum value of the supply voltage
of the recommended operating conditions.
When the supply voltage of a microcomputer falls below to the
minimum value of recommended operating conditions and re-
goes up (ex. battery exchange of an application product),
depending on the capacity value of the bypass capacitor added
to the power supply pin, the following case may cause program
failure (Figure 43);
supply voltage does not fall below to VRST-, and
its voltage re-goes up with no reset.
In such a case, please design a system which supply voltage is
once reduced below to VRST- and re-goes up after that.
(1) SVDE instruction
When the SVDE instruction is executed, the voltage drop deteciton
circuit is valid even after system enters into the power down mode.
The SVDE instruction can be executed only once.
In order to release the execution of the SVDE instruction, the sys-
tem reset is required.
Fig. 43 VDD and VRST–
VDD
Recommended
operatng condition
min.value
No reset
Program failure may occur.
VRST
+
VRST
–
VDD
Recommended
operatng condition
min.value
VRST
+
VRST
–
→ Normal operation
Reset
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