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參數(shù)資料
| 型號： | M34552G8HFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP48 |
| 封裝： | 7 X 10 MM, 0.65 MM PITCH, PLASTIC, QFP-48 |
| 文件頁數(shù)： | 139/143頁 |
| 文件大?。?/td> | 0K |
| 代理商： | M34552G8HFP |
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8: REGISTERS
S1D13505F00A HARDWARE FUNCTIONAL
EPSON
1-83
SPECIFICATION (X23A-A-001-12)
bit 7
HRTC Polarity Select
This bit selects the polarity of the HRTC pulse to the CRT.
When this bit = 1, the HRTC pulse is active high. When this bit = 0, the HRTC pulse is
active low.
bit 6
FPLINE Polarity Select
This bit selects the polarity of the FPLINE pulse to TFT/D-TFD or passive LCD.
When this bit = 1, the FPLINE pulse is active high for TFT/D-TFD and active low for
passive LCD. When this bit = 0, the FPLINE pulse is active low for TFT/D-TFD and
active high for passive LCD.
bits 3–0
HRTC/FPLINE Pulse Width Bits [3:0]
For CRT and TFT/D-TFD, these bits specify the pulse width of HRTC and FPLINE
respectively. For passive LCD, FPLINE is automatically created and these bits have no
effect.
HRTC/FPLINE pulse width (pixels) = (HRTC/FPLINE Pulse Width Bits [3:0] + 1)
× 8
The maximum HRTC pulse width is 128 pixels.
Note: This register must be programmed such that
(REG[05h] + 1)
≥ (REG[06h] + 1) + (REG[07h] bits [3:0] + 1)
REG[08h] bits 7–0 Vertical Display Height Bits [9:0]
REG[09h] bits 1–0 These bits specify the vertical display height.
Vertical display height (lines) = Vertical Display Height Bits [9:0] + 1
For CRT, TFT/D-TFD, and single passive LCD panel this register is programmed to:
(vertical resolution of the display) - 1,
e.g. EFh for a 240-line display.
For dual-panel passive LCD not in simultaneous display mode, this register is pro-
grammed to:
((vertical resolution of the display)/2) - 1, e.g. EFh for a 480-line display.
For all simultaneous display modes, this register is programmed to:
(vertical resolution of the CRT) - 1,
e.g. 1DFh for a 480-line CRT.
HRTC/FPLINE Pulse Width Register
REG[07h]
RW
HRTC
Polarity Select
FPLINE
Polarity Select
n/a
HRTC/FPLINE
Pulse Width Bit
3
HRTC/FPLINE
Pulse Width Bit
2
HRTC/FPLINE
Pulse Width Bit
1
HRTC/FPLINE
Pulse Width Bit
0
Table 8-4 FPLINE Polarity Selection
FPLINE Polarity Select
Passive LCD FPLINE Polarity
TFT/D-TFD FPLINE Polarity
0
active high
active low
1
active low
active high
Vertical Display Height Register 0
REG[08h]
RW
Vertical Dis-
play Height
Bit 7
Vertical Dis-
play Height
Bit 6
Vertical Dis-
play Height
Bit 5
Vertical Dis-
play Height
Bit 4
Vertical Dis-
play Height
Bit 3
Vertical Dis-
play Height
Bit 2
Vertical Dis-
play Height
Bit 1
Vertical Dis-
play Height
Bit 0
Vertical Display Height Register 1
REG[09h]
RW
n/a
Vertical Dis-
play Height
Bit 9
Vertical Dis-
play Height
Bit 8
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M34556G8HFP | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDSO42 |
| M34556M8-XXXFP | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO42 |
| M34556M8H-XXXFP | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO42 |
| M34556M4H-XXXFP | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO42 |
| M34559G6FP | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP52 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M34552M4H-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34552M4-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34552M8H-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34552M8-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34552MXH-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
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