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參數(shù)資料
| 型號(hào)： | M34552G8HFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP48 |
| 封裝： | 7 X 10 MM, 0.65 MM PITCH, PLASTIC, QFP-48 |
| 文件頁數(shù)： | 92/143頁 |
| 文件大小： | 0K |
| 代理商： | M34552G8HFP |
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Rev.3.02
Dec 22, 2006
page 50 of 142
REJ03B0023-0302
4552 Group
Program counter (PC) ..........................................................................................................
Address 0 in page 0 is set to program counter.
Interrupt enable flag (INTE) ..................................................................................................
Power down flag (P) .............................................................................................................
External 0 interrupt request flag (EXF0) ..............................................................................
Interrupt control register V1 ..................................................................................................
Interrupt control register V2 ..................................................................................................
Interrupt control register I1 ...................................................................................................
Timer 1 interrupt request flag (T1F) .....................................................................................
Timer 2 interrupt request flag (T2F) .....................................................................................
Timer 3 interrupt request flag (T3F) .....................................................................................
Watchdog timer flags (WDF1, WDF2) ..................................................................................
Watchdog timer enable flag (WEF) ......................................................................................
Timer control register PA ......................................................................................................
Timer control register W1 .....................................................................................................
Timer control register W2 .....................................................................................................
Timer control register W3 .....................................................................................................
Timer control register W4 .....................................................................................................
Clock control register MR .....................................................................................................
Clock control register RG .....................................................................................................
LCD control register L1 ........................................................................................................
LCD control register L2 ........................................................................................................
LCD control register L3 ........................................................................................................
LCD control register C1 ........................................................................................................
LCD control register C2 ........................................................................................................
Key-on wakeup control register K0 ......................................................................................
Key-on wakeup control register K1 ......................................................................................
Key-on wakeup control register K2 ......................................................................................
Pull-up control register PU0 .................................................................................................
Pull-up control register PU1 .................................................................................................
Port output structure control register FR0 ...........................................................................
Port output structure control register FR1 ...........................................................................
Port output structure control register FR2 ...........................................................................
Carry flag (CY) ......................................................................................................................
High-order bit reference enable flag (UPTF) .......................................................................
Register A .............................................................................................................................
Register B .............................................................................................................................
Register D .............................................................................................................................
Register E .............................................................................................................................
Register X .............................................................................................................................
Register Y .............................................................................................................................
Register Z .............................................................................................................................
Stack pointer (SP) ................................................................................................................
Operation source clock .......................................................... On-chip oscillator (operating)
Ceramic resonator circuit ..................................................................................... Operating
RC oscillation circuit ...................................................................................................... Stop
Quartz-crystal oscillator ........................................................................................ Operating
Fig. 40 Internal state at reset
(2) Internal state at reset
Figure 40 shows internal state at reset (they are the same after sys-
tem is released from reset). The contents of timers, registers, flags
and RAM except shown in Figure 40 are undefined, so set the ini-
tial value to them.
“” represents undefined.
00
000
0
(Interrupt disabled)
0
(Interrupt disabled)
0
(Interrupt disabled)
000
0
1
0
(Prescaler stopped)
0
(Timer 1 stopped)
0
(Timer 2 stopped)
0
(Timer 3 stopped)
0
(Timer LC stopped)
110
0
00
0
000
0
000
0
111
1
111
1
111
1
000
0
000
0
000
0
000
0
000
0
000
0
000
0
000
0
000
0
000
0
000
0
000
0
11
1
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