參數(shù)資料
型號(hào)： M34552G8HFP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP48
封裝： 7 X 10 MM, 0.65 MM PITCH, PLASTIC, QFP-48
文件頁數(shù)： 105/143頁
文件大小： 0K
代理商： M34552G8HFP
7: A.C. CHARACTERISTICS
1-52
EPSON
S1D13505F00A HARDWARE FUNCTIONAL
SPECIFICATION (X23A-A-001-12)
Table 7-18 FPM-DRAM Read/Write/Read-Write Timing
Symbol
Parameter
Min.
Max.
Units
t1
Internal memory clock period
40
ns
t2
Random read cycle REG[22h] bits 6-5 = 00
5 t1
ns
Random read cycle REG[22h] bits 6-5 = 01
4 t1
ns
Random read cycle REG[22h] bits 6-5 = 10
3 t1
ns
t3
RAS# precharge time (REG[22h] bits 3-2 = 00)
2 t1 - 3
ns
RAS# precharge time (REG[22h] bits 3-2 = 01)
1.45 t1 - 3
ns
RAS# precharge time (REG[22h] bits 3-2 = 10)
1 t1 - 3
ns
t4
RAS# to CAS# delay time (REG[22h] bit 4 = 1 and bits 3-2 = 00 or 10)
1.45 t1 - 3
ns
RAS# to CAS# delay time (REG[22h] bit 4 = 0 and bits 3-2 = 00 or 10)
2.45 t1 - 3
ns
RAS# to CAS# delay time (REG[22h] bit 4 = 1 and bits 3-2 = 01)
1 t1 - 3
ns
RAS# to CAS# delay time (REG[22h] bit 4 = 0 and bits 3-2 = 01)
2 t1 - 3
ns
t5
CAS# precharge time
0.45 t1 - 3
ns
t6
CAS# pulse width
0.45 t1 - 3
ns
t7
RAS# hold time
0.45 t1 - 3
ns
t8
Row address setup time (REG[22h] bits 3-2 = 00)
2 t1 - 3
ns
Row address setup time (REG[22h] bits 3-2 = 01)
1.45 t1 - 3
ns
Row address setup time (REG[22h] bits 3-2 = 10)
1 t1 - 3
ns
t9
Row address hold time (REG[22h] bits 3-2 = 00 or 10)
t1 - 3
ns
Row address hold time (REG[22h] bits 3-2 = 01)
0.45 t1 - 3
ns
t10
Column address setup time
0.45 t1 - 3
ns
t11
Column address hold time
0.45 t1 - 3
ns
t12
Read Command Setup (REG[22h] bit 4 = 0 and bits 3-2 = 00)
4.45 t1 - 3
ns
Read Command Setup (REG[22h] bit 4 = 0 and bits 3-2 = 01 or 10)
3.45 t1 - 3
ns
Read Command Setup (REG[22h] bit 4 = 1 and bits 3-2 = 00)
3.45 t1 - 3
ns
Read Command Setup (REG[22h] bit 4 = 1 and bits 3-2 = 01 or 10)
2.45 t1 - 3
ns
t13
Read Command Hold (REG[22h] bit 4 = 0 and bits 3-2 = 00)
4 t1 - 3
ns
Read Command Hold (REG[22h] bit 4 = 0 and bits 3-2 = 01 or 10)
3 t1 - 3
ns
Read Command Hold (REG[22h] bit 4 = 1 and bits 3-2 = 00)
3 t1 - 3
ns
Read Command Hold (REG[22h] bit 4 = 1 and bits 3-2 = 01 or 10)
2 t1 - 3
ns
t14
Read Data Setup referenced from CAS#
5
ns
t15
Bus Tri-State
3
t1 - 5
ns
t16
Write Command Setup
0.45 t1 - 3
ns
t17
Write Command Hold
0.45 t1 - 3
ns
t18
Write Data Setup
0.45 t1 - 3
ns
t19
Write Data Hold
0.45 t1 - 3
ns
t20
MD Tri-state
0.45 t1
0.45 t1 + 21
ns
t21
CAS# to WE# active during Read-Write cycle
0.45 t1 - 3
ns
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