參數(shù)資料
型號: M34506E4FP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, OTPROM, MICROCONTROLLER, PDSO20
封裝: 5.30 X 12.60 MM, 1.27 MM PITCH, PLASTIC, SOP-20
文件頁數(shù): 68/114頁
文件大?。?/td> 937K
代理商: M34506E4FP
Rev.2.00
Aug 28, 2006
page 54 of 119
7643 Group
REJ03B0054-0200
[USB endpoint x (x = 0 to 2) OUT Write Count Registers]
WRT_CNTR
This register contain the number of bytes in the endpoint x OUT
FIFO. This is read-only register. This register must be read after
the USB FCU has received a packet of data from the host.
When the OUT FIF0 is in double buffer mode, the CPU first reads
the received number of bytes of the former data packet. The next
CPU read can obtain that of the new data packet.
Fig. 48 Structure of USB endpoint x (x = 0 to 2) OUT write count registers
Low-order 8 bits of the number of bytes in endpoint x OUT FIFO
USB endpoint x OUT write count register (address 005D16)
WRT_CNT
b0
b7
[USB Endpoint x (x = 0 to 2) FIFO Register] USBFIFOx
These registers are the USB IN (transmit) and OUT (receive) FIFO
data registers. Write data to the corresponding register, and read
data from the corresponding register.
When the maximum packet size is equal to or less than half the
FIFO size, these registers function in double buffer mode and can
hold two packets of data. When the IN_PKT_RDY bit is “0” and
the TX_NOT_EMPTY bit is “1”, these bits indicate that one packet
of data is stored in the IN FIFO. When the OUT FIFO is in double
buffer mode, the OUT_PKT_RDY flag remains as “1” after the first
packet of data is read out (it actually goes to “0” and returns to “1”
after one
φ cycle).
Endpoint x IN/OUT FIFO
USB endpoint x FIFO register
(addresses 006016, 006116, 006216)
USBFIFOx
b0
b7
Fig. 49 Structure of USB endpoint x (x = 0 to 2) FIFO register
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