參數(shù)資料
型號: M34506E4FP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, OTPROM, MICROCONTROLLER, PDSO20
封裝: 5.30 X 12.60 MM, 1.27 MM PITCH, PLASTIC, SOP-20
文件頁數(shù): 37/114頁
文件大?。?/td> 937K
代理商: M34506E4FP
Rev.2.00
Aug 28, 2006
page 25 of 119
7643 Group
REJ03B0054-0200
Timer 1, Timer 2, Timer 3
Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for
each timer can be selected by timer 123 mode register.
q Timers 1, 2 Write Control
When the Timers 1, 2 Write Control Bit is “1” and the values are
written in the address of timers 1 and 2, the values are loaded only
in their latches. The values in the latches are loaded in timers 1
and 2 after timers 1 and 2 underflow.
When the Timers 1, 2 Write Control Bit is “0” and the values are
written in the address of timers 1 and 2, the values are loaded in
the timers 1 and 2 and their latches at the same time.
q Timers 1, 2 Output Control
A signal of which polarity is inverted each time the timer selected
by the TOUT Factor Select Bit underflows is output from the TOUT
pin. This is enabled by setting the TOUT Output Control Bit to “1”.
When the TOUT Output Active Edge Switch Bit is “0”, the TOUT pin
starts pulses output beginning at “H”; when this bit is “1”, the TOUT
pin starts pulses output beginning at “L”.
When using a timer in this mode, set the port P51 direction regis-
ter to output mode.
s Notes
q Timer 1 to Timer 3
Switching of the count sources of timers 1 to 3 does not affect the
values of reload latches. However, that may make count operation
started. Therefore, write values again in the order of timers 1, 2
and then timer 3 after their count sources have been switched.
q Timers 1, 2 Write Control
When the value is to be written in latch only, unexpected value
may be set in the timer if the writing in the latch and the timer un-
derflow are performed at the same timing.
Fig. 20 Structure of timer 123 mode register
Timer 123 mode register (address 002916)
T123M
TOUT factor select bit
0: Timer 1 output
1: Timer 2 output
Timer 1 count stop bit
0: Count start
1: Count stop
Timer 1 count source select bit
0 :
φ / 8
1 : f(XCIN) / 2
Timer 2 count source select bit
0 : Timer 1 output
1 :
φ
Timer 3 count source select bit
0 : Timer 1 output
1 :
φ / 8
TOUT output active edge switch bit
0 : Start at “H” output
1 : Start at “L” output
TOUT output control bit
0: TOUT output disabled
1: TOUT output enabled
Timers 1, 2 write control bit
0: Write value in latch and counter
1: Write value in latch only
b0
b7
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