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參數(shù)資料
| 型號： | M34506E4FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, MICROCONTROLLER, PDSO20 |
| 封裝： | 5.30 X 12.60 MM, 1.27 MM PITCH, PLASTIC, SOP-20 |
| 文件頁數(shù)： | 57/114頁 |
| 文件大小： | 937K |
| 代理商： | M34506E4FP |
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Rev.2.00
Aug 28, 2006
page 43 of 119
7643 Group
REJ03B0054-0200
USB Reception
Endpoint 0 to Endpoint 2 have OUT (receive) FIFOs individually.
Each endpoint’s FIFO is configured in following way:
Endpoint 0: 16-byte
Endpoint 1: 128-byte
Endpoint 2: Mode 0: 32-byte
Mode 1: 128-byte
When Endpoint 2 is used for data receive, the OUT FIFO size can
be selected. Endpoint 2 have 2 modes programmable IN-FIFO.
Each mode can be selected by the USB endpoint FIFO mode se-
lection register (address 005F16).
Data transmitted from the host-PC is stored in Endpoint x FIFO
(006016 to 006216). Every time the data is stored in the FIFO, the
internal OUT FIFO write pointer is increased by 1. When one com-
plete data packet is stored, the OUT_PKT_RDY flag is set to “1”
and the number of received data packets is stored in USB End-
point x OUT write count register. When the AUTO_CLR bit is “1”
and the received data is read out from the OUT FIFO, the
OUT_PKT_RDY flag is cleared to “0”. When the AUTO_CLR bit is
“1”, the OUT_PKT_RDY flag will not be cleared automatically by
the FIFO read; it must be cleared by software. (The AUTO-CLR bit
function is not applicable in Endpoint 0.)
When MAXP size
≤ (a half of OUT FIFO size), the OUT_FIFO can
receive 2 packets (double buffer). At this time, the OUT_ FIFO sta-
tus can be checked by the OUT_PKT_RDY flag. When the FIFO
holds two packets and one packet is read from the FIFO, the
OUT_PKT_RDY flag is not cleared even if it is set to “0”. (The flag
returns from “0” to “1” in one
φ cycle after the read-out). During
double buffer mode, the USB Endpoint x OUT write count register
holds the number of previously received packets. This count regis-
ter is updated after reading out one of packets in the OUT FIFO
and clearing the OUT_PKT_RDY flag to “0”.
TOGGLE Initialization
In order to initialize the data toggle sequence bit of the endpoint,
in other words, resetting the next data packet to DATA0; set the
TOGGLE_INT bit to “1” and then clear back to “0”.
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| M34508G4H-XXXFP | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO20 |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M34506M2 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34506M2-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES |
| M34506M4 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34506M4-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES |
| M34507E4FP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
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