參數(shù)資料
型號： M34502M4-XXXFP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, MICROCONTROLLER, PDSO24
封裝： 5.30 X 10.10 MM, 0.80 MM PITCH, PLASTIC, SSOP-24
文件頁數(shù)： 86/96頁
文件大?。?/td> 958K
代理商： M34502M4-XXXFP
87
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 2.5. Memory Expansion Mode and Microprocessor Mode Timing
(Vcc = 4.15 to 5.25V, Vss = 0V, Ta = -20 to 85°C unless otherwise noted)
Note :
Measurement conditions: Iohl =
±5ma, C
L = 50pF
Symbol
Parameter
Limits
Unit
Min.
Typ.
Max.
tc(
Φ)
Φ clock cycle time
83.33
ns
twh(
Φ)
Φ clock “H” pulse width
0.5*tc(
Φ)-5
ns
twl(
Φ)
Φ clock “L” pulse width
0.5*tc(
Φ)-5
ns
td(
Φ-AH)
Address bus AB15-AB8 delay time with respect to
Φ
31
ns
tv(
Φ-AH)
Address bus AB15-AB8 valid time with respect to
Φ
5ns
td(
Φ-AL)
Address bus AB7-AB0 delay time with respect to
Φ
33
ns
tv(
Φ-AL)
Address bus AB7-AB0 valid time with respect to
Φ
5ns
td(
Φ-WR)
WR delay time
6ns
tv(
Φ-WR)
WR valid time
3
ns
td(
Φ-RD)
RD delay time
6ns
tv(
Φ-RD)
RD valid time
3
ns
td(
Φ-SYNC)
SYNCOUT delay time
6ns
tv(
Φ-SYNC)
SYNCOUT valid time
4ns
td(
Φ-DMA)
DMAOUT delay time
25
ns
tv(
Φ-DMA)
DMAOUT valid time
5ns
tsu(RDY-
Φ)
RDY setup time with respect to
Φ
21
ns
th(
Φ-RDY)
RDY hold time with respect to
Φ
0ns
tsu(HOLD-
Φ)
HOLD setup time
21
ns
th(
Φ-HOLD)
HOLD hold time
0ns
td(
Φ-HLDAL)
HLDAL delay time
25
ns
tv(
Φ-HLDAH)
HLDAH delay time
25
ns
tsu(DB-
Φ)
Data bus setup time with respect to
Φ
7ns
th(
Φ-DB)
Data bus hold time with respect to
Φ
0ns
td(
Φ-DB)
Data bus delay time with respect to
Φ
22
ns
tv(
Φ-DB)
Data bus valid time with respect to
Φ (Note)
13
ns
twl(WR)
WR pulse width
0.5*tc(
Φ)-5
ns
twl(RD)
RD pulse width
0.5*tc(
Φ)-5
ns
td(AH-WR)
WR delay time after stable address AB15-AB8
0.5*tc(
Φ)-28
ns
td(AL-WR)
WR delay time after stable address AB7-AB0
0.5*tc(
Φ)-30
ns
tv(WR-AH)
Address bus AB15-AB8 valid time with respect to WR
0ns
tv(WR-AL)
Address bus AB7-AB0 valid time with respect to WR
0
ns
td(AH-RD)
RD delay time after stable address AB15-AB8
0.5*tc(
Φ)-28
ns
td(AL-RD)
RD delay time after stable address AB7-AB0
0.5*tc(
Φ)-30
ns
tv(RD-AH)
Address bus AB15-AB8 valid time with respect to RD
0ns
tv(RD-AL)
Address bus AB7-AB0 valid time with respect to RD
0ns
tsu(RDY-WR)
RDY setup time with respect to WR
27
ns
th(WR-RDY)
RDY hold time with respect to WR
0
ns
tsu(RDY-RD)
RDY setup time with respect to RD
27
ns
th(RD-RDY)
RDY hold time with respect to RD
0
ns
tsu(DB-RD)
Data bus setup time with respect to RD
13
ns
th(RD-DB)
Data bus hold time with respect to RD
0ns
td(WR-DB)
Data bus delay time with respect to WR
20
ns
tv(WR-DB)
Data bus valid time with respect to WR Note
10
ns
tr(D+), tr(D-)
USB output rise time, CL=50 pF
4
20
ns
tf (D+), tf(D-)
USB output fall time, CL=50 pF
4
20
ns
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