參數(shù)資料
型號(hào)： M34502M4-XXXFP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, MICROCONTROLLER, PDSO24
封裝： 5.30 X 10.10 MM, 0.80 MM PITCH, PLASTIC, SSOP-24
文件頁(yè)數(shù)： 36/96頁(yè)
文件大小： 958K
代理商： M34502M4-XXXFP
41
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.19 UART
This chip contains two identical UARTs. Each UART
has the following main features:
Clock selection ..................................
F or SCSGCLK
Prescaler selection ............... x1/x8/x32/x256 divisions
............................................ (both
F and SCSGCLK)
Baud rate .......................................... (at
F = 12MHz)
......................... 11.4 bits/second-750 Kbytes/second
Error detection ...................................... parity/framing/
...................................................... overrun/error sum
Parity .................................................. odd/even/none
Stop bits ........................................................... 1 or 2
Character length .................................... 7, 8, or 9 bits
Transmit/receive buffer .................................. 2 stages
...................................................... (double buffering)
Handshaking ............................... Clear-to-Send (CTS)
............................................. Request-to-Send (RTS)
Interrupt generation conditions ............. Transmit Buffer
..................................... Empty or Transmit Complete
...........................................................Receive Buffer
.................................................... Receive Error Sum
Address ............... mode for multi-receiver environment
The following descriptions apply to both UARTs.
The UART receives parallel data from the core or
DMAC, converts it into serial data, and transmits the
results to the send data output terminal UTXDx. The
UART receives serial data from an external source
through the receive data input URXDx, converts it into
parallel data, and makes it available to the core or
DMAC. The UART can detect parity, overrun, and
framing errors in the input stream and report the appro-
priate status information. A double buffering
configuration is used for the UART’s transmit and re-
ceive
operations.
This
double
buffering
is
accomplished by the use of a transmit buffer and
transmit shift register on the transmit side and the re-
ceive buffer and receive shift register on the receive
side.
The UART supports an address mode for use in a
multi-receiver environment where an address is sent
before each message to designate which UART or
UARTs are to wake-up and receive the message. Fig-
ure 1.41 is a block diagram of the UART. It is valid for
both UART1 and UART2.
Fig. 1.41. UART Block Diagram
UART Mode
Register
UART Control
Transmit
Data Bus
Transmit
UART Status
Data Bus
UxMOD
Register
UxSTS
UxCON
Buffer
Shift Register
ST/STP/PA
Generator
Receive
Buffer Register
Stop and Start
Detect
Data Format
Bit Counter
Data Format
Bit Counter
Prescaler
/1/8/32/256
Clock Set
Tx Enable
Tx Buffer Empty
TBE
TIS = "0"
TIS = "1"
TCM
Transmit line to UTXDx
Receive line from URXDx
Receive Buffer Full Interrupt
Receive Error Interrupt
Rx Complete
Rx Status Errors
Tx Complete
LE 1,0; PEN; STB
PS 1,0
CLKSEL
Φ
SCSGCLK
Transmit Interrupt
Baud Rate Generator
Rx Enable
Receive
Shift Register
To RTSx
RTS Control
Register
From CTSx
RTS_SEL
CTS_SEL
Data Bus
___
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