參數(shù)資料
型號： M34502M4-XXXFP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, MICROCONTROLLER, PDSO24
封裝： 5.30 X 10.10 MM, 0.80 MM PITCH, PLASTIC, SSOP-24
文件頁數(shù)： 16/96頁
文件大?。?/td> 958K
代理商： M34502M4-XXXFP
23
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.14.5.7 Port 8
Port 8 is an 8-bit general purpose I/O port that can be
configured to access special second functions. The
port can be set up in any configuration in all three pro-
cessor modes.
Port P80
This pin is multiplexed with the SIO SRDY signal and
the UART2 TxD signal. When UART2 is in transmit
mode, the pin acts as the TxD output signal. When
the pin is not being used as the UART2 TxD output
and bit 4 of the SIO control register 1 (SIOCON1) is a
“1”, the port acts as the SIO SRDY output signal. If
during this function, the SIO is configured in slave
mode, this pin acts as a slave input from a master.
See section 1.18 for more SIO information.
Port P81
This pin is multiplexed with the SIO SCLK signal and
the UART2 RxD signal. When UART2 is in receive
mode, the pin acts as the RxD input signal. When the
pin is not being used as the UART2 RxD input and bit
2 of the SIO control register 1 (SIOCON1) is a “1”, the
port acts as the SIO SCLK signal. In this mode a “1”
in bit 6 of SIOCON1 configures the pin to output
SCLK whereas a “0” configures the pin to input SCLK.
Port P82
This pin is multiplexed with the SIO SRxD signal and
the UART2 CTS signal. When bit 5 of the UART2
control register (U2CON) is a “1”, the port acts as the
CTS input signal. When the pin is not being used as
the UART2 CTS input and bit 2 of the SIO control reg-
ister 2 (SIOCON2) is a “1”, the port acts as the SIO
SRxD input signal.
Port P83
This pin is multiplexed with the SIO STxD signal and
the UART2 RTS signal. When bit 6 of the UART2
control register (U2CON) is a “1”, the port acts as the
RTS output signal. When the pin is not being used as
the UART2 RTS output and bit 3 of the SIO control
register 1 (SIOCON1) is a “1”, the port acts as the
SIO STxD output signal.
Fig. 1.20. Port P80, P81, P82, P83 Block Diagram
Direction Register
Data Bus
Port Latch
SIO Ready Output
UART2 TxD Output
UART2 Transmit Control Bit
SRDY Output Selection Bit
SIO slave control
SIO Slave mode selection bit
Direction Register
Data Bus
Port Latch
SIO Clock Output
SIO Port Selection Bit
SIO Clock Selection Bit
SIO clock input
UART2 receive control bit
UART2 receive control Bit
UART2 RxD input
SIO Clock Selectio Bit
n
Direction Register
Data Bus
Port Latch
UART2 CTS Enable Bit
SIO Receive Enable Bit
SIO RxD input
UART2 CTS Enable Bit
UART2 CTS input
Direction Register
Data Bus
Port Latch
SIO TxD Output
UART2 RTS Output
SIO Port Selection Bit
Transmit Complete Signal
P-Channel Output Disable Bit
UART2 RTS Enable Bit
Port P80
Port P81
Port P82
Port P83
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