參數(shù)資料
型號： M34502M4-XXXFP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, MICROCONTROLLER, PDSO24
封裝： 5.30 X 10.10 MM, 0.80 MM PITCH, PLASTIC, SSOP-24
文件頁數(shù)： 19/96頁
文件大?。?/td> 958K
代理商： M34502M4-XXXFP
26
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.15 INTERRUPT CONTROL UNIT
This section details a specialized peripheral, the inter-
rupt control unit (ICU).
This series supports a maximum of 23 maskable inter-
rupts, one software interrupts, and one reset vector
that is treated as a non-maskable interrupt.
Table 1.6 describes the interrupt registers. See Table
1.7 for the interrupt sources, jump destination ad-
dresses, interrupt priorities, and section references
for the interrupt request sources.
Table 1.7. Interrupt Vector
Table 1.6. Interrupt Registers
Address
Description
Acronym and
Value at Reset
000216
Interrupt request register A
IREQA=00
000316
Interrupt request register B
IREQB=00
000416
Interrupt request register C
IREQC=00
000516
Interrupt control register A
ICONA=00
000616
Interrupt control register B
ICONB=00
000716
Interrupt control register C
ICONC=00
001116
Interrupt polarity selection
register
IPOL=00
Jump Destination
Storage Address
(Vector Address)
Remarks
Priority
Interrupt
High-order
Byte
Low-order
Byte
Reference
1
RSRV1
FFFF
FFFE
Reserved for factory use
2
RSRV2
FFFD
FFFC
Reserved for factory use
3
RESET
FFFB
FFFA
User RESET (Non-Maskable)
4
USB
FFF9
FFF8
USB Function Interrupt
0
LSB
Section 1.21.2.1
5
SOF
FFF7
FFF6
USB SOF Interrupt
1
Section 1.21.2.2
6
INT0
FFF5
FFF4
External Interrupt 0
2
Section 1.15.1
7
INT1
FFF3
FFF2
External Interrupt 1
3
Section 1.15.1
8
DMA1
FFF1
FFF0
DMAC Channel 0 Interrupt
4
Section 1.23
9
DMA2
FFEF
FFEE
DMAC Channel 1 Interrupt
5
Section 1.23
10
U1RBF
FFED
FFEC
UART1 Receiver Buffer Full
6
Section 1.19.4.2
11
U1TX
FFEB
FFEA
UART1 Transmit Interrupt
7
MSB
IREQA
&
ICONA
Section 1.19.4.1
12
U1ES
FFE9
FFE8
UART1 Error Sum Interrupt
0
LSB
Section 1.19.4.2
13
U2RBF
FFE7
FFE6
UART2 Receiver Buffer Full
1
Section 1.19.4.2
14
U2TX
FFE5
FFE4
UART2 Transmit Interrupt
2
Section 1.19.4.1
15
U2ES
FFE3
FFE2
UART2 Error Sum Interrupt
3
Section 1.19.4.2
16
TX
FFE1
FFE0
Timer X Interrupt
4
Section 1.17
17
TY
FFDF
FFDE
Timer Y Interrupt
5
Section 1.17
18
T1
FFDD
FFDC
Timer 1 Interrupt
6
Section 1.17
19
T2
FFDB
FFDA
Timer 2 Interrupt
7
MSB
IREQB
&
ICONB
Section 1.17
20
T3
FFD9
FFD8
Timer 3 Interrupt
0
LSB
Section 1.17
21
CNTR0
FFD7
FFD6
External CNTR0 Interrupt
1
Section 1.17.1.2
22
CNTR1
FFD5
FFD4
External CNTR1 Interrupt
2
Section 1.17.2
23
SIO
FFD3
FFD2
SIO Interrupt
3
Section 1.18
24
IBF
FFD1
FFD0
Input Buffer Full Interrupt
4
Section 1.22
25
OBE
FFCF
FFCE
Output Buffer Empty Interrupt
5
Section 1.22
26
KEY
FFCD
FFCC
Key-on Wake Up
6
MSB
IREQC
&
ICONC
Corresponding
Register
Assignment
Section 1.16
27
BRK
FFCB
FFCA
BRK Instruction (Non-Maskable)
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