參數(shù)資料
型號： M34502M4-XXXFP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, MICROCONTROLLER, PDSO24
封裝： 5.30 X 10.10 MM, 0.80 MM PITCH, PLASTIC, SSOP-24
文件頁數(shù)： 72/96頁
文件大?。?/td> 958K
代理商： M34502M4-XXXFP
74
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.24.1 Frequency Synthesizer Circuit
The Frequency Synthesizer Circuit generates a 48MHz
clock needed by the USB block and a clock fSYN that
are both a multiple of the external input reference
clock fIN. A block diagram of the circuit is shown in
Figure 1.91.
The frequency synthesizer consists of a prescaler, fre-
quency multiplier macro, a frequency divider macro,
and four registers, namely FSM1, FSM2, FSC and
FSD. Two multiply registers (FSM1, FSM2) control the
frequency multiply amount. Clock fIN is prescaled us-
ing FSM2 to generate fPIN. fPIN is multiplied using
FSM1 to generate an fVCO clock which is then divided
using FSD to produce the clock fSYN. The fVCO clock
is optimized for 48 MHz operation and is buffered and
sent out of the frequency synthesizer block as signal
fUSB. This signal is used by the USB block. The clock
block diagram is shown in Figure 1.92.
Clock fPIN is a divided down version of clock fIN, which
can be either f(Xin) or f(XCin). The default clock after re-
set is fXin. The relationship between fPIN and the clock
input to the prescaler (fIN) is as follows:
fPIN = fIN/2(n+1) where n is a decimal number between
0 and 254. (See Figure 1.95).
Setting FSM2 to 255 disables the prescaler and fPIN =
fIN.
Data Bus
FSM2
FSM1
FSC
FSD
006E
006D
006C
006F
Frequency
Multiplier
Frequency
Divider
8
B
it
Bit
fIN
fVCO
fSYN
fUSB
Prescaler
8
B
it
fPIN
The relationship between fPIN, fVCO, fSYN, and fUSB is
as follows:
fVCO = fPIN x 2(n+1) where n is the decimal equivalent
of the value loaded in FSM1. (See Figure 1.94).
n must be chosen such that fVCO equals 48 MHz.
fSYN = fVCO / 2(m+1) where m is the decimal equiva-
lent of the value loaded in FSD. (See Figure 1.96).
Setting m=255 disables the divider and disables fSYN.
fUSB is a buffered version of fVCO, i.e., FSD has no ef-
fect on fUSB.
Setting USB control register bit 5 to “0” disables fUSB
by tri-stating the buffer.
The FSC0 bit in the FSC Register (FSC) enables the
frequency synthesizer block. When disabled (FSC0 =
“0”), fVCO is held at either a high or low state. When
the frequency synthesizer control bit is active (FSC0
= “1”), a lock status (LS = “1”) indicates that fSYN and
fVCO are the correct frequency. The LS and FSCO
control bits in the FSC register are shown in Figure
1.93.
When using the frequency synthesizer, a low-pass fil-
ter must be connected to the LPF pin.
Once the frequency synthesizer is enabled, a delay of
2-5ms is recommended before the output of the fre-
quency synthesizer is used. This is done to allow the
output to stabilize. It is also recommended that none
of the registers be modified once the frequency syn-
thesizer is enabled as it will cause the output to be
temporarily (2-5ms) unstable.
Fig. 1.91. Frequency Synthesizer Circuit
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