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參數(shù)資料
| 型號： | M30L0R8000T0ZAQE |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | AB 35C 7#12,28#16 PIN RECP |
| 中文描述： | 256兆位（16Mb的x16插槽，多銀行，多層次，多突發(fā)）1.8V電源快閃記憶體 |
| 文件頁數(shù)： | 7/83頁 |
| 文件大?。?/td> | 1363K |
| 代理商： | M30L0R8000T0ZAQE |
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M30L0R8000T0, M30L0R8000B0
SUMMARY DESCRIPTION
The M30L0R8000T0 and M30L0R8000B0 are 256
Mbit (16 Mbit x16) non-volatile Flash memories
that may be erased electrically at block level and
programmed in-system on a Word-by-Word basis
using a 1.7V to 2.0V V
DD
supply for the circuitry
and a 1.7V to 2.0V V
DDQ
supply for the Input/Out-
put pins. An optional 9V V
PP
power supply is pro-
vided to speed up factory programming.
The device features an asymmetrical block archi-
tecture and is based on a multi-level cell technolo-
gy.
The M30L0R8000x0 has an array of 259 blocks,
and is divided into 16 Mbit banks. There are 15
banks each containing 16 main blocks of 64
KWords, and one parameter bank containing 4 pa-
rameter blocks of 16 KWords and 15 main blocks
of 64 KWords.
The Multiple Bank Architecture allows Dual Oper-
ations, while programming or erasing in one bank,
read operations are possible in other banks. Only
one bank at a time is allowed to be in program or
erase mode. It is possible to perform burst reads
that cross bank boundaries. The bank architecture
is summarized in
Table 2.
, and the memory maps
are shown in
Figure 4.
The Parameter Blocks are
located at the top of the memory address space for
the M30L0R8000T0, and at the bottom for the
M30L0R8000B0.
Each block can be erased separately. Erase can
be suspended, in order to perform a program or
read operation in any other block, and then re-
sumed. Program can be suspended to read data
at any memory location except for the one being
programmed, and then resumed. Each block can
be programmed and erased over 100,000 cycles
using the supply voltage V
DD
. There is a Buffer
Enhanced Factory programming command avail-
able to speed up programming.
Program and erase commands are written to the
Command Interface of the memory. An internal
Program/Erase Controller takes care of the tim-
ings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified in the
Status Register. The command set required to
control the memory is consistent with JEDEC stan-
dards.
The device supports Synchronous Burst Read and
Asynchronous Read from all blocks of the memory
array; at power-up the device is configured for
Asynchronous Read. In Synchronous Burst Read
mode, data is output on each clock cycle at fre-
quencies of up to 54MHz. The Synchronous Burst
Read operation can be suspended and resumed.
The device features an Automatic Standby mode.
When the bus is inactive during Asynchronous
Read operations, the device automatically switch-
es to the Automatic Standby mode. In this condi-
tion the power consumption is reduced to the
standby value and the outputs are still driven.
The M30L0R8000x0 features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency, enabling in-
stant code and data protection. All blocks have
three levels of protection. They can be locked and
locked-down individually preventing any acciden-
tal programming or erasure. There is an additional
hardware protection against program and erase.
When V
PP
≤
V
PPLK
all blocks are protected against
program or erase. All blocks are locked at power-
up.
The device includes 17 Protection Registers and 2
Protection Register locks, one for the first Protec-
tion Register and the other for the 16 One-Time-
Programmable (OTP) Protection Registers of 128
bits each. The first Protection Register is divided
into two segments: a 64 bit segment containing a
unique device number written by ST, and a 64 bit
segment One-Time-Programmable (OTP) by the
user. The user programmable segment can be
permanently protected.
Figure 5.
, shows the Pro-
tection Register Memory Map.
The M30L0R8000x0 is offered in a Stacked
TFBGA88 8x10mm - 8x10 active ball array,
0.8mm pitch package.
In addition to the standard version, the packages
are also available in Lead-free version, in compli-
ance with JEDEC Std J-STD-020B, the ST ECO-
PACK 7191395 Specification, and the RoHS
(Restriction of Hazardous Substances) directive.
All packages are compliant with Lead-free solder-
ing processes.
The devices are supplied with all the bits erased
(set to ’1’).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M30L0R8000B0ZAQE | 256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
| M30L0R8000B0ZAQF | CAP 0.1UF 50V 10% X7R DIP-2 BULK S-MIL-C-39014 |
| M30L0R8000B0ZAQT | 256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
| M30L0R8000B0ZAQ | 256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
| M30L0R8000T0 | 256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M30L0R8000T0ZAQF | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
| M30L0R8000T0ZAQT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
| M30L40C | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:Dual Common-Cathode Schottky Rectifier |
| M30L40C-E3/4W | 功能描述:肖特基二極管與整流器 40 Volt 30 Amp Dual Common-Cathode RoHS:否 制造商:Skyworks Solutions, Inc. 產(chǎn)品:Schottky Diodes 峰值反向電壓:2 V 正向連續(xù)電流:50 mA 最大浪涌電流: 配置:Crossover Quad 恢復(fù)時間: 正向電壓下降:370 mV 最大反向漏泄電流: 最大功率耗散:75 mW 工作溫度范圍:- 65 C to + 150 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOT-143 封裝:Reel |
| M30L45C-E3/4W | 功能描述:肖特基二極管與整流器 45 Volt 30 Amp Dual Common-Cathode RoHS:否 制造商:Skyworks Solutions, Inc. 產(chǎn)品:Schottky Diodes 峰值反向電壓:2 V 正向連續(xù)電流:50 mA 最大浪涌電流: 配置:Crossover Quad 恢復(fù)時間: 正向電壓下降:370 mV 最大反向漏泄電流: 最大功率耗散:75 mW 工作溫度范圍:- 65 C to + 150 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOT-143 封裝:Reel |
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