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參數(shù)資料
| 型號： | LXT388LE |
| 英文描述： | PCM TRANSCEIVER|DUAL|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC |
| 中文描述： | 的PCM收發(fā)器|雙|優(yōu)稅PCM-30/E-1 |的CMOS | QFP封裝| 100引腳|塑料 |
| 文件頁數(shù)： | 32/80頁 |
| 文件大?。?/td> | 1112K |
| 代理商： | LXT388LE |
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LXT384
—
Octal T1/E1/J1 Transceiver
32
Datasheet
2.7.2
Digital Loopback
The digital loopback function is available in software mode only. When selected, the transmit clock
and data inputs (TCLK, TPOS & TNEG) are looped back and output on the RCLK, RPOS &
RNEG pins (see
Figure 9
). The data presented on TCLK, TPOS & TNEG is also output on the
TTIP & TRING pins. Note: signals on the RTIP & RRING pins are ignored during digital
loopback.
2.7.3
Remote Loopback
During remote loopback (see
Figure 10
), the RCLK, RPOS & RNEG outputs routed to the transmit
circuits and output on the TTIP & TRING pins. Note: input signals on the TCLK, TPOS & TNEG
pins are ignored during remote loopback.
Note:
In data recovery mode, the pulse template cannot be guaranteed while in a remote loopback.
2.7.4
Transmit All Ones (TAOS)
In Hardware mode, the TAOS mode is set by pulling TCLK High for more than 16 MCLK cycles.
In software mode, TAOS mode is set by asserting the corresponding bit in the TAOS Register. In
addition, automatic ATS insertion (in case of LOS) may be set using the ATS Register. Note: the
TAOS generator uses MCLK as a timing reference, therefore TAOS doesn
’
t work in data recovery
mode. In order to assure that the output frequency is within specification limits, MCLK must have
the applicable stability. DLOOP does not function when TAOS is active.
Figure 9. Digital Loopback
Timing &
Control
Timing
Recovery
TTIP
TRING
RTIP
RRING
RCLK
RPOS
RNEG
TCLK
TPOS
TNEG
* If Enabled
JA*
JA*
H
E
H
D
Figure 10. Remote Loopback
TCLK
TPOS
TNEG
TTIP
TRING
RTIP
RRING
* If Enabled
RCLK
RPOS
RNEG
Timing &
Control
Timing
Recovery
JA*
H
E
H
D
JA*
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