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參數(shù)資料
| 型號(hào)： | LXT388LE |
| 英文描述： | PCM TRANSCEIVER|DUAL|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC |
| 中文描述： | 的PCM收發(fā)器|雙|優(yōu)稅PCM-30/E-1 |的CMOS | QFP封裝| 100引腳|塑料 |
| 文件頁數(shù)： | 16/80頁 |
| 文件大小： | 1112K |
| 代理商： | LXT388LE |
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LXT384
—
Octal T1/E1/J1 Transceiver
16
Datasheet
21
22
23
24
25
26
27
28
G2
H3
H2
J4
J3
J2
J1
K1
LOOP0/D0
LOOP1/D1
LOOP2/D2
LOOP3/D3
LOOP4/D4
LOOP5/D5
LOOP6/D6
LOOP7/D7
DI/O
DI/O
DI/O
DI/O
DI/O
DI/O
DI/O
DI/O
Loopback Mode Select/Parallel Data bus Input &Output.
Host Mode
When a non-multiplexed microprocessor interface is selected, these
pins function as a bi-directional 8-bit data port.
When a multiplexed microprocessor interface is selected, these pins
carry both bi-directional 8-bit data and address inputs A0 -A7.
In serial Mode, D0-7 should be grounded.
Hardware Mode
In hardware mode, the LXT384 works in normal operation if this pin is
left open (unconnected).
The LXT384 enters remote loopback mode, if this pin is Low. In this
mode, data on TPOS and TNEG is ignored and data received on RTIP
and RRING is looped around and retransmitted on TTIP and TRING.
Note: in data recovery mode, the pulse template cannot be guaranteed
while in a remote loopback.
The LXT384 enters analog local loopback mode, if this pin is High. In
this mode, data received on RTIP and RRING is ignored and data
transmitted on TTIP and TRING is internally looped around and routed
back to the receive inputs.
Note:
When these inputs are left open, they stay in a high impedance
state. Therefore, the layout design should not route signals with
fast transitions near the LOOP pins. This practice will minimize
capacitive coupling.
29
L1
TCLK1
DI
Transmit Clock Input.
30
30
31
31
L2
L2
L3
L3
TPOS1
TDATA1
TNEG1
UBS1
DI
DI
DI
DI
Transmit Positive Data Input.
Transmit Data Input.
Transmit Negative Data Input.
Unipolar/Bipolar Select Input.
32
M1
RCLK1
DO
Receive Clock Output.
33
33
34
34
M2
M2
M3
M3
RPOS1
RDATA1
RNEG1
BPV1
DO
DO
DO
DO
Receive Positive Data Output.
Receive Data Output.
Receive Negative Data Output.
Bipolar Violation Detect Output.
35
K3
LOS1
DO
Loss of Signal Output.
36
N1
TCLK0
DI
Transmit Clock Input.
37
37
38
38
N2
N2
N3
N3
TPOS0
TDATA0
TNEG0
UBS0
DI
DI
DI
DI
Transmit Positive Data Input.
Transmit Data Input.
Transmit Negative Data Input.
Unipolar/Bipolar Select Input.
39
P1
RCLK0
DO
Receive Clock Output.
40
40
41
41
P2
P2
P3
P3
RPOS0
RDATA0
RNEG0
BPV0
DO
DO
DO
DO
Receive Positive Data.
Receive Data Output.
Receive Negative Data.
Bipolar Violation Detect.
42
K4
LOS0
DO
Loss of Signal Output.
Table 1. LXT384 Pin Description (Sheet 6 of 12)
Pin #
QFP
Ball #
PBGA
Symbol
I/O
1
Description
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output
S: Power Supply; N.C.: Not Connected.
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