參數(shù)資料
型號: LXT384LE
元件分類: 通信、網(wǎng)絡(luò)模塊及開發(fā)工具
英文描述: Telecomm/Datacomm
中文描述: 電信/數(shù)據(jù)通信
文件頁數(shù): 61/80頁
文件大?。?/td> 1112K
代理商: LXT384LE
Octal T1/E1/J1 Transceiver
LXT384
Datasheet
61
TCLK to TPOS/TNEG hold time
Tht
20
-
-
ns
Delay time OE Low to driver High Z
Toez
-
-
1
μ
s
Delay time TCLK Low to driver High Z
Ttz
50
60
75
μ
s
Figure 18. Transmit Clock Timing Diagram
Table 45. Receive Timing Characteristics (Sheet 1 of 2)
Parameter
Sym
Min.
Typ
Max
Unit
Test Condition
Clock recovery capture range
E1
±80
ppm
Relative to nominal
frequency
MCLK = ±100 ppm
T1
±180
ppm
Receive clock duty cycle
1
Rckd
40
50
60
%
Receive clock pulse width
1
E1
Tpw
447
488
529
ns
T1
Tpw
583
648
713
ns
Receive clock pulse width Low time
E1
Tpwl
203
244
285
ns
T1
Tpwl
259
324
389
ns
Receive clock pulse width High time
E1
Tpwh
203
244
285
ns
T1
Tpwh
259
324
389
ns
Rise/fall time
4
Tr
20
ns
@ CL=15 pF
RPOS/RNEG pulse width (MCLK=H)
2
E1
Tpwdl
200
244
300
ns
T1
Tpwdl
250
324
400
ns
RPOS/RNEG to RCLK rising setup time
E1
Tsur
200
244
ns
T1
200
324
ns
1. RCLK duty cycle widths will vary depending on extent of received pulse jitter displacement. Maximum and
minimum RCLK duty cycles are for worst case jitter conditions (0.2UI displacement for E1 per ITU G.823).
2. Clock recovery is disabled in this mode.
3. If MCLK = H the receive PLLs are replaced by a simple EXOR circuit.
4. For all digital outputs.
Table 44. Transmit Timing Characteristics (Sheet 2 of 2)
Parameter
Sym
Min.
Typ
Max
Unit
Test Condition
TPOS
TNEG
TCLK
tHT
tSUT
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