參數(shù)資料
型號(hào)： LXT384LE
元件分類： 通信、網(wǎng)絡(luò)模塊及開(kāi)發(fā)工具
英文描述： Telecomm/Datacomm
中文描述： 電信/數(shù)據(jù)通信
文件頁(yè)數(shù)： 5/80頁(yè)
文件大?。?/td> 1112K
代理商： LXT384LE
Datasheet
5
Octal T1/E1/J1 Line Interface Unit
—
LXT384
36
37
Low Quad Flat Packages (LQFP) Dimensions....................................................78
Plastic Ball Grid Array (PBGA) Package Dimensions.........................................79
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
LXT384 Pin Description.......................................................................................11
Line Length Equalizer Inputs...............................................................................27
Jitter Attenuation Specifications..........................................................................30
Operation Mode Summary..................................................................................34
Microprocessor Interface Selection.....................................................................35
Serial and Parallel Port Register Addresses.......................................................38
Register Bit Names .............................................................................................39
ID Register, ID (00h) ...........................................................................................40
Analog Loopback Register, ALOOP (01h) ..........................................................40
Remote Loopback Register, RLOOP (02h).........................................................40
TAOS Enable Register, TAOS (03h)...................................................................40
LOS Status Monitor Register, LOS (04h)............................................................41
DFM Status Monitor Register, DFM (05h)...........................................................41
LOS Interrupt Enable Register, LIE (06h) ...........................................................41
DFM Interrupt Enable Register, DIE (07h)..........................................................41
LOS Interrupt Status Register, LIS (08h) ............................................................41
DFM Interrupt Status Register, DIS (09h)...........................................................41
Software Reset Register, RES (0Ah)..................................................................42
Performance Monitoring Register, MON (0Bh) ...................................................42
Digital Loopback Register, DL (0Ch)...................................................................42
LOS/AIS Criteria Register, LCS (0Dh) ................................................................42
Automatic TAOS Select Register, ATS (0Eh) .....................................................42
Global Control Register, GCR (0Fh) ...................................................................43
Pulse Shaping Indirect Address Register, PSIAD (10h)......................................43
Pulse Shaping Data Register, PSDAT (11h).......................................................44
Output Enable Register, OER (12h)....................................................................44
AIS Status Monitor Register, AIS (13h)...............................................................44
AIS Interrupt Enable Register, AISIE (14h).........................................................44
AIS Interrupt Status Register, AISIS (15h)..........................................................45
TAP State Description.........................................................................................46
Boundary Scan Register (BSR)...........................................................................49
Analog Port Scan Register (ASR).......................................................................52
Device Identification Register (IDR)....................................................................53
Instruction Register (IR) ......................................................................................54
Absolute Maximum Ratings.................................................................................54
Recommended Operating Conditions.................................................................55
DC Characteristics ..............................................................................................55
E1 Transmit Transmission Characteristics..........................................................56
E1 Receive Transmission Characteristics...........................................................57
T1 Transmit Transmission Characteristics..........................................................58
T1 Receive Transmission Characteristics...........................................................58
Jitter Attenuator Characteristics..........................................................................59
Analog Test Port Characteristics.........................................................................60
Transmit Timing Characteristics..........................................................................60
Receive Timing Characteristics...........................................................................61
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