- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369885 > LXT384LE Telecomm/Datacomm PDF資料下載
參數(shù)資料
| 型號： | LXT384LE |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 20/80頁 |
| 文件大?。?/td> | 1112K |
| 代理商： | LXT384LE |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁
LXT384
—
Octal T1/E1/J1 Transceiver
20
Datasheet
88
H12
MOT/INTL/
CODEN
DI
Motorola/Intel/Codec Enable Select Input.
Host Mode:
When Low, the host interface is configured for Motorola
microcontrollers. When High, the host interface is configured for Intel
microcontrollers.
Hardware Mode:
Determines the line encode/decode selection when in unipolar mode.
When Low, B8ZS/HDB3 encoders/decoders are enabled for T1/E1
respectively. When High, enables AMI encoder/decoder (transparent
mode).
89
H11
GND1
S
Ground (Core).
90
H14
VCC1
S
Power (Core).
91
G11
GNDIO1
S
Ground (I/O).
92
G14
VCCIO1
S
Power (I/O).
93
G13
AT2
AO
JTAG Analog Output Test Port 2.
94
H13
AT1
AI
JTAG Analog Input Test Port 1.
95
G12
TRST
JTAG Controller Reset Input.
Input is used to reset the JTAG
controller. TRST is pulled up internally and may be left disconnected.
96
F11
TMS
DI
JTAG Test Mode Select Input.
Used to control the test logic state
machine. Sampled on rising edge of TCK. TMS is pulled up internally
and may be left disconnected.
97
F14
TCK
DI
JTAG Clock Input.
Clock input for JTAG. Connect to GND when not
used.
98
F13
TDO
DO
JTAG Data Output.
Test Data Output for JTAG. Used for reading all
serial configuration and test data from internal test logic. Updated on
falling edge of TCK.
99
F12
TDI
DI
JTAG Data Input.
Test Data input for JTAG. Used for loading serial
instructions and data into internal test logic. Sampled on rising edge of
TCK. TDI is pulled up internally and may be left disconnected.
100
D14
TCLK5
DI
Transmit Clock Input.
101
101
102
102
D13
D13
D12
D12
TPOS5
TDATA5
TNEG5
UBS5
DI
DI
DI
DI
Transmit Positive Data Input.
Transmit Data Input.
Transmit Negative Data Input.
Unipolar/Bipolar Select Input.
103
C14
RCLK5
DO
Receive Clock Output.
104
104
105
105
C13
C13
C12
C12
RPOS5
RDATA5
RNEG5
BPV5
DO
DO
DO
DO
Receive Positive Data Output.
Receive Data Output.
Receive Negative Data Output.
Bipolar Violation Detect Output.
106
E12
LOS5
DO
Loss of Signal Output.
107
B14
TCLK4
DI
Transmit Clock Input.
Table 1. LXT384 Pin Description (Sheet 10 of 12)
Pin #
QFP
Ball #
PBGA
Symbol
I/O
1
Description
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output
S: Power Supply; N.C.: Not Connected.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LXT386BE | PCM TRANSCEIVER|QUAD|CEPT PCM-30/E-1|CMOS|BGA|160PIN|PLASTIC |
| LXT386LE | PCM TRANSCEIVER|QUAD|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC |
| LXT388LE | PCM TRANSCEIVER|DUAL|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC |
| LXT400JE | Hermetically Sealed, 3.3V, High Speed, High CMR, Logic Gate Optocoupler |
| LXT6155LE | Telecomm/Datacomm |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXT386 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:QUAD T1/E1/J1 Transceiver |
| LXT386BE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM TRANSCEIVER|QUAD|CEPT PCM-30/E-1|CMOS|BGA|160PIN|PLASTIC |
| LXT386LE | 制造商:LEVEL1 功能描述: |
| LXT388LE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM TRANSCEIVER|DUAL|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC |
| LXT400 | 制造商:LVL1 制造商全稱:LVL1 功能描述:All Rate Extended Range Switched 56/DDS Transceiver |
發(fā)布緊急采購，3分鐘左右您將得到回復。