參數(shù)資料
型號(hào): LV8572AVX
英文描述: Real-Time Clock
中文描述: 實(shí)時(shí)時(shí)鐘
文件頁數(shù): 5/24頁
文件大小: 353K
代理商: LV8572AVX
General Description
(Continued)
The LV8571A’s interrupt structure provides four basic types
of interrupts: Periodic, Alarm/Compare, Timer, and Power
Fail. Interrupt mask and status registers enable the masking
and easy determination of each interrupt.
One dedicated general purpose interrupt output is provided.
A second interrupt output is available on the Multiple Func-
tion Output (MFO) pin. Each of these may be selected to
generate an interrupt from any source. Additionally, the
MFO pin may be programmed to be either as oscillator out-
put or Timer 0’s output.
Pin Description
CS, RD, WR (Inputs):
These pins interface to
m
P control
lines. The CS pin is an active low enable for the read and
write operations. Read and Write pins are also active low
and enable reading or writing to the TCP. All three pins are
disabled when power failure is detected. However, if a read
or write is in progress at this time, it will be allowed to com-
plete its cycle.
A0–A4 (Inputs):
These 5 pins are for register selection.
They individually control which location is to be accessed.
These inputs are disabled when power failure is detected.
OSC IN (Input): OSC OUT (Output):
These two pins are
used to connect the crystal to the internal parallel resonant
oscillator. The oscillator is always running when power is
applied to V
BB
and V
CC
, and the correct crystal select bits in
the Real Time Mode Register have been set.
MFO (Output):
The multi-function output can be used as a
second interrupt output for interrupting the
m
P. This pin can
also provide an output for the oscillator or the internal Timer
0. The MFO output can be programmed active high or low,
open drain or push-pull. If in battery backed mode and a
pull-up resistor is attached, it should be connected to a volt-
age no greater than V
BB
. This pin is configured open drain
during battery operation (V
BB
l
V
CC
).
INTR (Output):
The interrupt output is used to interrupt the
processor when a timing event or power fail has occurred
and the respective interrupt has been enabled. The INTR
output can be programmed active high or low, push-pull or
open drain. If in battery backed mode and a pull-up resistor
is attached, it should be connected to a voltage no greater
than V
BB
. This pin is configured open drain during battery
operation (V
BB
l
V
CC
).
D0–D7 (Input/Output):
These 8 bidirectional pins connect
to the host
m
P’s data bus and are used to read from and
write to the TCP. When the PFAIL pin goes low and a write
is not in progress, these pins are at TRI-STATE.
PFAIL (Input):
In battery backed mode, this pin can have a
digital signal applied to it via some external power detection
logic. When PFAIL
e
logic 0 the TCP goes into a lockout
mode, in a minimum of 30
m
s or a maximum of 63
m
s unless
lockout delay is programmed. In the single power supply
mode, this pin is not useable as an input and should be tied
to V
CC
. Refer to section on Power Fail Functional Descrip-
tion.
V
BB
(Battery Power Pin):
This pin is connected to a back-
up power supply. This power supply is switched to the inter-
nal circuitry when the V
CC
becomes lower than V
BB
. Utiliz-
ing this pin eliminates the need for external logic to switch in
and out the back-up power supply. If this feature is not to be
used then this pin must be tied to ground, the TCP pro-
grammed for single power supply only, and power applied to
the V
CC
pin.
V
CC
:
This is the main system power pin.
GND:
This is the common ground power pin for both V
BB
and V
CC
.
Connection Diagram
Dual-In-Line
TL/F/11416–5
Top View
Order Number LV8571AN
See NS Package Number N24C
5
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