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參數(shù)資料
| 型號： | LU3X54FT |
| 英文描述： | QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| 中文描述： | 四場效應管（快速以太網(wǎng)收發(fā)器）的10Base-T/100Base-TX/FX |
| 文件頁數(shù)： | 4/54頁 |
| 文件大?。?/td> | 677K |
| 代理商： | LU3X54FT |
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4
Lucent Technologies Inc.
LU3X54FT
QUAD-FET for 10Base-T/100Base-TX/FX
Data Sheet
July 2000
Features
(continued)
100 Mbits/s FX Transceiver
I
Compatible with IEEE802.3U 100Base-FX standard
I
Reuses existing twisted-pair I/O pins for compatible
fiber-optic transceiver pseudo-ECL (PECL) data:
— No additional data pins required
— Reuses existing LU3X54FT pins for fiber-optic sig-
nal detect (FOSD) inputs
I
Fiber mode automatically configures port:
— Disables autonegotiation
— Disables 10Base-T
— Enables 100Base-FX remote fault signaling
— Disables MLT-3 encoder/decoder
— Disables scrambler/descrambler
I
FX mode enable is pin- or register-selectable on an
individual per-port basis.
General
I
Autonegotiation (IEEE802.3u, clause 28):
— Fast link pulse (FLP) burst generator
— Arbitration function
I
Bused interfaces:
— Supports either separate 10 Mbits/s and
100 Mbits/s multiport repeaters (100 Mbits/s
MII and 10 Mbits/s serial data stream), or single-
chip multispeed repeaters
— Connects ports to either the 10 Mbits/s or
100 Mbits/s buses controlled by autonegotiation
— Separate TX_EN, RX_EN, CRS, and COL pins for
each port
— Drivers on bused signal can drive up to eight
LU3X54FTs (32 ports)
I
Supports the station management protocol and
frame format (clause 22):
— Basic and extended registers
— Supports next-page function
— Operates up to 12.5 MHz
— Accepts preamble suppression
— Maskable status interrupts
I
Supports the following management functions via
pins if MII station management is unavailable:
— Speed select
— Carrier integrity enable
— Encoder/decoder bypass
— Scrambler/descrambler bypass
— Full duplex
— No link pulse mode
— Carrier sense select
— Autonegotiation
— 10 Mbits/s repeater reference select
— Internal 20 MHz clock synthesizer
— FX mode select
I
Single 25 MHz crystal input or 25 MHz clock input,
optional 20 MHz clock input
I
Supports half- and full-duplex operations
I
Provides six status signals:
— Receive activity
— Transmit activity
— Full duplex
— Collision/jabber
— Link integrity
— Speed indication
I
Optional LED pulse stretching
I
Per-channel powerdown mode for 10 Mbits/s and
100 Mbits/s operation
I
Loopback for 10 Mbits/s and 100 Mbits/s operation
I
Internal pull-up or pull-down resistors to set default
powerup mode
I
0.35
μ
m,
low-power CMOS technology
I
208-pin SQFP or 208-pin SQFPH
I
Single 5 V power supply
Description
Bused MII Mode
The LU3X54FT has been designed for operation in two
basic system interface modes of operation:
I
Normal MII Mode (Four Separate MII Ports).
The
separate mode provides four independent RJ-45 to
MII ports and is similar to having four independent
10/100 transceivers.
I
Bused MII Mode.
This mode is designed specifically
for repeater applications to save pins. In bused
mode:
— Data from all of the ports operating at 100 Mbits/s
will be internally bused to system interface port A
(100 Mbits/s MII interface).
— Data from all of the ports operating at 10 Mbits/s
will be internally bused to system interface port B
(7-pin 10 Mbits/s serial interface).
The LU3X54FT will automatically detect the speed of
each port (10 Mbits/s or 100 Mbits/s) and route the
data to the appropriate port.
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| LU3X54FT | Quad-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX(應用于10基數(shù)-T和100基數(shù)-TX/FX的四快速以太網(wǎng)收發(fā)器) |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LU3X54FTL | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208 | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208 |
| LU3X54FTL-HS208-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208-DB | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208-DB |
| LU400 | 制造商:MA-COM 制造商全稱:M/A-COM Technology Solutions, Inc. 功能描述:NEMA Cabinet Legs |
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