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參數(shù)資料
| 型號： | LU3X54FT |
| 英文描述： | QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| 中文描述： | 四場效應(yīng)管（快速以太網(wǎng)收發(fā)器）的10Base-T/100Base-TX/FX |
| 文件頁數(shù)： | 25/54頁 |
| 文件大?。?/td> | 677K |
| 代理商： | LU3X54FT |
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Lucent Technologies Inc.
25
Data Sheet
July 2000
LU3X54FT
QUAD-FET for 10Base-T/100Base-TX/FX
171—168
RXLED[D:A]/
FX_MODE_EN[D:A]
I/O
Receive LED[D:A].
This pin indicates receive activity. External buffers
are necessary to drive the LEDs.
FX Mode Enable.
At powerup or reset,
when pulled high through a
4.7 k
resistor, this pin will enable the FX mode (10Base-T and
100Base-TX disabled). When pulled low, it will enable 10Base-T and
100Base-TX modes (100Base-FX mode disabled). These pins are
ORed with register 29, bit 0 [29.0].
These pins have internal 50 k
pull-down resistors.
Collision LED.
This pin indicates collision occurrence. External buffers
are necessary to drive the LEDs.
176—173
COLED[D:A]
O
Channels A and B have internal 50 k
pull-down resistors but not
channels C and D.
Link LED[D]
. This pin indicates good link status on port D. External
buffers are necessary to drive the LEDs.
PHY Address 2.
At powerup or reset, this pin is used to set the PHY
address bit 2.
190
LINKLED[D]/
PHYADD[2]
I/O
If this pin is pulled high through a 50 k
resistor, it will set PHYADD[2]
to a 1. If this pin is pulled low through a 50 k
resistor, it will set
PHYADD[2] to a 0.
Link LED[C].
This pin indicates good link status on port C. External
buffers are necessary to drive the LEDs.
PHY Address 1.
At powerup or reset, this pin is used to set the PHY
address bit 1.
189
LINKLED[C]/
PHYADD[1]
I/O
If this pin is pulled high through a 50 k
resistor, it will set PHYADD[1]
to a 1. If this pin is pulled low through a 50 k
resistor, it will set
PHYADD[1] to a 0.
Link LED[B].
This pin indicates good link status on port B. External
buffers are necessary to drive the LEDs.
PHY Address 0.
At powerup or reset, this pin may be used to set the
PHY address bit 0.
188
LINKLED[B]/
PHYADD[0]
I/O
If this pin is pulled high through a 50 k
resistor, it will set PHYADD[0]
to a 1. If this pin is pulled low through a 50 k
resistor, it will set
PHYADD[0] to a 0.
Link LED[A].
This pin indicates good link status on port A. External
buffers are necessary to drive the LEDs.
No Link Pulse.
This pin is used at powerup or reset to select the
NO_LP function of register 30, bit 0 for all four channels by pulling this
pin high through a 4.7 k
resistor. This input and the register bit [30.0]
are ORed together.
187
LINKLED[A]/
NO_LP
I/O
This pin has an internal 50 k
pull-down resistor to set the default to
normal link pulse ON mode.
Pin Information
(continued)
Pin Descriptions
(continued)
Table 7. Miscellaneous Pins
(continued)
Pin
Signal
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LU3X54FTL | QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTL-HS208-DB | QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FT | Quad-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX(應(yīng)用于10基數(shù)-T和100基數(shù)-TX/FX的四快速以太網(wǎng)收發(fā)器) |
| LU5X34F | Quad Gigabit Ethernet Transceiver |
| LU5X34F | Quad Gigabit Ethernet Transceiver(千兆位以太網(wǎng)四收發(fā)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LU3X54FTL | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208 | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208 |
| LU3X54FTL-HS208-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208-DB | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208-DB |
| LU400 | 制造商:MA-COM 制造商全稱:M/A-COM Technology Solutions, Inc. 功能描述:NEMA Cabinet Legs |
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