參數(shù)資料
型號： LU3X54FT
英文描述： QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX
中文描述： 四場效應管（快速以太網(wǎng)收發(fā)器）的10Base-T/100Base-TX/FX
文件頁數(shù)： 16/54頁
文件大?。?/td> 677K
代理商： LU3X54FT
LU3X54FT
QUAD-FET for 10Base-T/100Base-TX/FX
Data Sheet
July 2000
16
Lucent Technologies Inc.
Pin Information
(continued)
Pin Descriptions
This section describes the LU3X54FT signal pins. Note that any register bit referenced includes the register num-
ber and bit position. For example, register bit [29.8] is register 29, bit 8.
Table 3. MII/Serial Interface Pins in Normal MII Mode (Four Separate MII Ports)
Pin
100
67
150
127
Signal
COL[D:A]
Type
O
Description
Collision Detect.
This signal signifies in half-duplex mode that a collision
has occurred on the network. COL is asserted high whenever there is
transmit and receive activity on the UTP media. COL is the logical AND of
TX_EN and receive activity, and is an asynchronous output. When
SERIAL_SEL is high and in 10Base-T mode, this signal indicates the jab-
ber timer has expired.
Carrier Sense.
When CRS_SEL is low, this signal is asserted high when
either the transmit or receive medium is nonidle. This signal remains
asserted throughout a collision condition. When CRS_SEL is high, CRS is
asserted on receive activity only. CRS_SEL is set via the MII management
interface or the CRS_SEL pin.
Receive Clock.
25 MHz clock output in 100 Mbits/s mode, 2.5 MHz output
in 10 Mbits/s nibble mode, 10 MHz in 10 Mbits/s serial mode. RX_CLK has
a worst-case 45/55 duty cycle. RX_CLK provides the timing reference for
the transfer of RX_DV, RXD, and RX_ER signals.
Receive Data
. 4-bit parallel data outputs that are synchronous to RX_CLK.
When RX_ER[D:A] is asserted high in 100 Mbits/s mode, an error code will
be presented on RXD[3:0][D:A] where appropriate. The codes are as fol-
lows:
99
66
149
126
CRS[D:A]
O
104
71
154
131
109
76
159
136
108
75
158
135
107
74
157
134
105
72
155
132
101
68
151
128
103
70
153
130
RX_CLK[D:A]
O
RXD[3:0][D:A]
O
I
Packet errors: ERROR_CODES = 2h.
I
Link errors: ERROR_CODES = 3h. (Packet and link error codes will only
be repeated if registers [29.9] and [29.8] are enabled.)
I
Premature end errors: ERROR_CODES = 4h.
I
Code errors: ERROR_CODES = 5h.
When SERIAL_SEL is active-high and 10 Mbits/s mode is selected, RXD[0]
is used for data output and RXD[3:1] are 3-stated.
RX_DV[D:A]
O
Receive Data Valid.
When this pin is high, it indicates the LU3X54FT is
recovering and decoding valid nibbles on RXD[3:0], and the data is syn-
chronous with RX_CLK. RX_DV is synchronous with RX_CLK. This pin is
not used in serial 10 Mbits/s mode.
Receive Error.
When high, RX_ER indicates the LU3X54FT has detected
a coding error in the frame presently being transferred. RX_ER is synchro-
nous with RX_CLK.
Receive Data[4].
When encoder/decoder bypass (ENC_DEC_BYPASS) is
selected through the MII management interface, this output serves as the
RXD[4] output. This pin is only valid when the LU3X54FT is in 100 Mbits/s
mode.
RX_ER[D:A]/
RXD[4][D:A]
O
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