參數(shù)資料
型號: LPC2930FBD208
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: ARM9 flashless microcontroller with CAN, LIN, and USB
中文描述: 32-BIT, MROM, 125 MHz, RISC MICROCONTROLLER, PQFP208
封裝: 28 X 28 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT459-1, LQFP-208
文件頁數(shù): 35/98頁
文件大?。?/td> 643K
代理商: LPC2930FBD208
LPC2930_3
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 16 April 2010
35 of 98
NXP Semiconductors
LPC2930
ARM9 microcontroller with CAN, LIN, and USB
All I/O defaults to input at reset to avoid any possible bus conflicts.
6.11.6.1
Functional description
The general-purpose I/O provides individual control over each bidirectional port pin. There
are two registers to control I/O direction and output level. The inputs are synchronized to
achieve stable read-levels.
To generate an open-drain output, set the bit in the output register to the desired value.
Use the direction register to control the signal. When set to output, the output driver
actively drives the value on the output: when set to input the signal floats and can be
pulled up internally or externally.
6.11.6.2
Pin description
The six GPIO ports in the LPC2930 have the pins listed below. The GPIO pins are
combined with other functions on the port pins of the LPC2930.
Table 18
shows the GPIO
pins.
Table 18.
Symbol
GPIO0 pin[31:0]
GPIO1 pin[31:0]
GPIO2 pin[27:0]
GPIO3 pin[15:0]
GPIO4 pin[24:0]
GPIO5 pin[19:0]
6.11.6.3
Clock description
The GPIO modules are clocked by several clocks, all of which are derived from
BASE_SYS_CLK; CLK_SYS_PESS and CLK_SYS_GPIOx (x = 0, 1, 2, 3, 4, 5), see
Section 6.6.2
. Note that each GPIO has its own CLK__SYS_GPIOx branch clock for
power management. The frequency of all clocks CLK_SYS_GPIOx is identical to
CLK_SYS_PESS since they are derived from the same base clock BASE_SYS_CLK.
6.12 Networking subsystem
6.12.1
CAN gateway
Controller Area Network (CAN) is the definition of a high-performance communication
protocol for serial data communication. The two CAN controllers in the LPC2930 provide a
full implementation of the CAN protocol according to the
CAN specification version 2.0B
.
The gateway concept is fully scalable with the number of CAN controllers, and always
operates together with a separate powerful and flexible hardware acceptance filter.
The key features are:
Supports 11-bit as well as 29-bit identifiers.
Double receive buffer and triple transmit buffer.
Programmable error-warning limit and error counters with read/write access.
Arbitration-lost capture and error-code capture with detailed bit position.
Single-shot transmission (i.e. no re-transmission).
GPIO pins
Pin name
P0[31:0]
P1[31:0]
P2[27:0]
P3[15:0]
P4[24:0]
P5[19:0]
Direction
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
Description
GPIO port x pins 31 to 0
GPIO port x pins 31 to 0
GPIO port x pins 27 to 0
GPIO port x pins 15 to 0
GPIO port x pins 24 to 0
GPIO port x pins 19 to 0
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