參數(shù)資料
型號: LPC2930FBD208
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: ARM9 flashless microcontroller with CAN, LIN, and USB
中文描述: 32-BIT, MROM, 125 MHz, RISC MICROCONTROLLER, PQFP208
封裝: 28 X 28 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT459-1, LQFP-208
文件頁數(shù): 16/98頁
文件大小: 643K
代理商: LPC2930FBD208
LPC2930_3
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 16 April 2010
16 of 98
NXP Semiconductors
LPC2930
ARM9 microcontroller with CAN, LIN, and USB
6.5 Reset, debug, test, and power description
6.5.1
Reset and power-up behavior
The LPC2930 contains external reset input and internal power-up reset circuits. This
ensures that a reset is extended internally until the oscillators have reached a stable state.
See
Section 8
for trip levels of the internal power-up reset circuit
1
. See
Section 9
for
characteristics of the several start-up and initialization times.
Table 4
shows the reset pin.
Table 4.
Symbol
RST
At activation of the RST pin, the JTAGSEL pin is sensed as logic LOW. If this is the case
the LPC2930 is assumed to be connected to debug hardware, and internal circuits
re-program the source for the BASE_SYS_CLK to be the crystal oscillator instead of the
Low-Power Ring Oscillator (LP_OSC). This is required because the clock rate when
running at LP_OSC speed is too low for the external debugging environment.
6.5.2
Reset strategy
The LPC2930 contains a central module, the Reset Generator Unit (RGU) in the Power,
Clock and Reset Subsystem (PCRSS), which controls all internal reset signals towards
the peripheral modules. The RGU provides individual reset control as well as the
monitoring functions needed for tracing a reset back to source.
6.5.3
IEEE 1149.1 interface pins (JTAG boundary-scan test)
The LPC2930 contains boundary-scan test logic according to IEEE 1149.1, also referred
to in this document as Joint Test Action Group (JTAG). The boundary-scan test pins can
be used to connect a debugger probe for the embedded ARM processor. Pin JTAGSEL
selects between boundary-scan mode and debug mode.
Table 5
shows the boundary-
scan test pins.
Table 5.
Symbol
JTAGSEL
6.5.3.1
ETM/ETB
The ETM provides real-time trace capability for deeply embedded processor cores. It
outputs information about processor execution to a trace buffer. A software debugger
allows configuration of the ETM using a JTAG interface and displays the trace information
that has been captured in a format that a user can easily understand. The ETB stores
trace data produced by the ETM.
1.
Only for 1.8 V power sources
Reset pin
Direction
IN
Description
external reset input, active LOW; pulled up internally
IEEE 1149.1 boundary-scan test and debug interface
Description
TAP controller select input. LOW level selects ARM debug mode and HIGH level
selects boundary scan; pulled up internally
test reset input; pulled up internally (active LOW)
test mode select input; pulled up internally
test data input, pulled up internally
test data output
test clock input
TRST
TMS
TDI
TDO
TCK
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