參數(shù)資料
型號(hào): LPC2930FBD208
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: ARM9 flashless microcontroller with CAN, LIN, and USB
中文描述: 32-BIT, MROM, 125 MHz, RISC MICROCONTROLLER, PQFP208
封裝: 28 X 28 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT459-1, LQFP-208
文件頁(yè)數(shù): 21/98頁(yè)
文件大?。?/td> 643K
代理商: LPC2930FBD208
LPC2930_3
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 16 April 2010
21 of 98
NXP Semiconductors
LPC2930
ARM9 microcontroller with CAN, LIN, and USB
Table 8.
Base clock
6.7 External Static Memory Controller (SMC)
The LPC2930 contains an external Static Memory Controller (SMC) which provides an
interface for external (off-chip) memory devices.
Key features are:
Supports static memory-mapped devices including RAM, ROM, flash, burst ROM and
external I/O devices
Asynchronous page-mode read operation in non-clocked memory subsystems
Asynchronous burst-mode read access to burst-mode ROM devices
Independent configuration for up to eight banks, each up to 16 MB
Programmable bus-turnaround (idle) cycles (one to 16)
Programmable read and write wait states (up to 32), for static RAM devices
Programmable initial and subsequent burst-read wait state for burst-ROM devices
Programmable write protection
Programmable burst-mode operation
Programmable external data width: 8 bits, 16 bits or 32 bits
Programmable read-byte lane enable control
6.7.1
Description
The SMC simultaneously supports up to eight independently configurable memory banks.
Each memory bank can be 8 bits, 16 bits or 32 bits wide and is capable of supporting
SRAM, ROM, burst-ROM memory, or external I/O devices.
A separate chip select output is available for each bank. The chip select lines are
configurable to be active HIGH or LOW. Memory-bank selection is controlled by memory
addressing.
Table 9
shows how the 32-bit system address is mapped to the external bus
memory base addresses, chip selects, and bank internal addresses.
Table 9.
32-bit
system
address bit
field
31 to 29
CGU1 base clock and branch clock overview
Branch clock name
Parts of the device clocked by this
branch clock
CLK_OUT pin
USB clock
USB OTG I
2
C clock
BASE_OUT_CLK
BASE_USB_CLK
BASE_USB_I2C_CLK
CLK_OUT_CLK
CLK_USB_CLK
CLK_USB_I2C_CLK
External memory-bank address bit description
Symbol
Description
BA[2:0]
external static-memory base address (three most significant bits);
the base address can be found in the memory map; see
Ref. 1
. This
field contains ‘010’ when addressing an external memory bank.
chip select address space for eight memory banks; see
Ref. 1
.
always ‘00’; other values are ‘mirrors’ of the 16 MB bank address.
16 MB memory banks address space
28 to 26
25 and 24
23 to 0
CS[2:0]
-
A[23:0]
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