參數(shù)資料
型號： LPC2926FBD144
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： ARM9 microcontroller with CAN, LIN, and USB
中文描述： 32-BIT, FLASH, 125 MHz, RISC MICROCONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT486-1, LQFP-144
文件頁數(shù)： 78/95頁
文件大小： 1855K
代理商： LPC2926FBD144
LPC2926_27_29
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 5 — 28 September 2010
78 of 95
NXP Semiconductors
LPC2926/2927/2929
ARM9 microcontroller with CAN, LIN, and USB
9.6 Dynamic characteristics: external static memory
[1]
All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at T
amb
= 85
°
C ambient
temperature on wafer level. Cased products are tested at T
amb
= 25
°
C (final testing). Both pre-testing and final testing use correlated
test conditions to cover the specified temperature and power supply voltage range.
[2]
When the byte lane select signals are used to connect the write enable input (8 bit devices), t
CSHBLSH
=
0.5
×
T
CLCL
.
When the byte lane select signals are used to connect the write enable input (8 bit devices), t
CSLBLSL
= t
CSLWEL
.
For 16 and 32 bit devices.
[3]
[4]
Table 42.
V
DD(CORE)
= V
DD(OSC_PLL)
; V
DD(IO)
= 2.7 V to 3.6 V; V
DDA(ADC3V3)
= 3.0 V to 3.6 V; all voltages are measured with respect to
ground.
[1]
Symbol
Parameter
Conditions
Min
External static memory interface dynamic characteristics
Typ
Ma
x
100 ns
20.
5
24.
9
Unit
T
CLCL
t
a(R)int
clock cycle time
internal read access time
8
-
-
-
ns
t
a(W)int
internal write access time
-
-
ns
Read cycle parameters
t
CSLAV
CS LOW to address valid
time
t
OELAV
OE LOW to address valid
time
t
CSLOEL
CS LOW to OE LOW time
t
su(DQ)
data input/output set-up
time
t
h(D)
data input hold time
t
CSHOEH
CS HIGH to OE HIGH time
t
BLSLBLSH
BLS LOW to BLS HIGH time
5
2.5
-
ns
5
WSTOEN
×
T
CLCL
2.5
WSTOEN
×
T
CLCL
-
ns
-
11
0 + WSTOEN
×
T
CLCL
16
-
22
ns
ns
0
-
-
2.5
0
(WST1
WSTOEN + 1)
×
T
CLCL
(WST1
WSTOEN + 1)
×
T
CLCL
0 + WSTOEN
×
T
CLCL
5
-
-
ns
ns
ns
t
OELOEH
OE LOW to OE HIGH time
-
-
ns
t
BLSLAV
BLS LOW to address valid
time
Write cycle parameters
t
CSHBLSH
CS HIGH to BLS HIGH time
t
CSLWEL
CS LOW to WE LOW time
t
CSLBLSL
CS LOW to BLS LOW time
t
WELDV
WE LOW to data valid time
t
CSLDV
CS LOW to data valid time
t
WELWEH
WE LOW to WE HIGH time
-
-
ns
[2]
-
-
-
-
0.5
-
0
(WSTWEN + 0.5)
×
T
CLCL
WSTWEN
×
T
CLCL
(WSTWEN + 0.5)
×
T
CLCL
0.1
(WST2
WSTWEN + 1)
×
T
CLCL
(WST2
WSTWEN + 2)
×
T
CLCL
-
-
-
-
0.3
-
ns
ns
ns
ns
ns
ns
[3]
t
BLSLBLSH
BLS LOW to BLS HIGH time
[4]
-
-
ns
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