參數(shù)資料
型號: LPC2926FBD144
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: ARM9 microcontroller with CAN, LIN, and USB
中文描述: 32-BIT, FLASH, 125 MHz, RISC MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT486-1, LQFP-144
文件頁數(shù): 35/95頁
文件大?。?/td> 1855K
代理商: LPC2926FBD144
LPC2926_27_29
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 5 — 28 September 2010
35 of 95
NXP Semiconductors
LPC2926/2927/2929
ARM9 microcontroller with CAN, LIN, and USB
[1]
Direction of SPIx SCS and SPIx SCK pins depends on master or slave mode. These pins are output in
master mode, input in slave mode.
[2]
In slave mode there is only one chip select input pin, SPIx SCS0. The other chip selects have no function in
slave mode.
6.13.5.3
Clock description
The SPI modules are clocked by two different clocks; CLK_SYS_PESS and CLK_SPIx
(x = 0, 1, 2), see
Section 6.7.2
. Note that each SPI has its own CLK_SPIx branch clock for
power management. The frequency of all clocks CLK_SPIx is identical as they are derived
from the same base clock BASE_CLK_SPI. The register interface towards the system bus
is clocked by CLK_SYS_PESS. The serial-clock rate divisor is clocked by CLK_SPIx.
The SPI clock frequency can be controlled by the CGU. In master mode the SPI clock
frequency (CLK_SPIx) must be set to at least twice the SPI serial clock rate on the
interface. In slave mode CLK_SPIx must be set to four times the SPI serial clock rate on
the interface.
6.13.6
General-purpose I/O
The LPC2926/2927/2929 contains four general-purpose I/O ports located at different
peripheral base addresses. In the 144-pin package all four ports are available. All I/O pins
are bidirectional, and the direction can be programmed individually. The I/O pad behavior
depends on the configuration programmed in the port function-select registers.
The key features are:
General-purpose parallel inputs and outputs
Direction control of individual bits
Synchronized input sampling for stable input-data values
All I/O defaults to input at reset to avoid any possible bus conflicts
6.13.6.1
Functional description
The general-purpose I/O provides individual control over each bidirectional port pin. There
are two registers to control I/O direction and output level. The inputs are synchronized to
achieve stable read-levels.
To generate an open-drain output, set the bit in the output register to the desired value.
Use the direction register to control the signal. When set to output, the output driver
actively drives the value on the output: when set to input the signal floats and can be
pulled up internally or externally.
6.13.6.2
Pin description
The five GPIO ports in the LPC2926/2927/2929 have the pins listed below. The GPIO pins
are combined with other functions on the port pins of the LPC2926/2927/2929.
Table 19
shows the GPIO pins.
SPIx SCK
SPIx SDI
SPIx SDO
SCKx
SDIx
SDOx
IN/OUT
IN
OUT
SPIx clock
[1]
SPIx data input
SPIx data output
Table 18.
Symbol
SPI pins
…continued
Pin name
Direction
Description
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