參數(shù)資料
型號(hào): LPC2926FBD144
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: ARM9 microcontroller with CAN, LIN, and USB
中文描述: 32-BIT, FLASH, 125 MHz, RISC MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT486-1, LQFP-144
文件頁(yè)數(shù): 24/95頁(yè)
文件大?。?/td> 1855K
代理商: LPC2926FBD144
LPC2926_27_29
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 5 — 28 September 2010
24 of 95
NXP Semiconductors
LPC2926/2927/2929
ARM9 microcontroller with CAN, LIN, and USB
Table 11.
32-bit
system
address bit
field
31 to 29
Table 12.
CS[2:0]
000
001
010
011
100
101
110
111
6.9.2
Pin description
The external static-memory controller module in the LPC2926/2927/2929 has the
following pins, which are combined with other functions on the port pins of the
LPC2926/2927/2929.
Table 13
shows the external memory controller pins.
Table 13.
Symbol
EXTBUS CSx
EXTBUS BLSy
EXTBUS WE
EXTBUS OE
EXTBUS A[23:0] A[23:0]
EXTBUS D[31:0] D[31:0]
6.9.3
Clock description
The External Static Memory Controller is clocked by CLK_SYS_SMC, see
Section 6.7.2
.
6.9.4
External memory timing diagrams
A timing diagram for reading from external memory is shown in
Figure 5
. The relationship
between the wait-state settings is indicated with arrows.
External memory-bank address bit description
Symbol
Description
BA[2:0]
external static-memory base address (three most significant bits);
the base address can be found in the memory map; see
Ref. 1
. This
field contains ‘010’ when addressing an external memory bank.
chip select address space for eight memory banks; see
Ref. 1
.
always ‘00’; other values are ‘mirrors’ of the 16 MB bank address.
16 MB memory banks address space
28 to 26
25 and 24
23 to 0
CS[2:0]
-
A[23:0]
External static-memory controller banks
Bank
bank 0
bank 1
bank 2
bank 3
bank 4
bank 5
bank 6
bank 7
External memory controller pins
Pin name
CSx
BLSy
WE
OE
Direction
OUT
OUT
OUT
OUT
OUT
IN/OUT
Description
memory-bank x select, x runs from 0 to 7
byte-lane select input y, y runs from 0 to 3
write enable (active LOW)
output enable (active LOW)
address bus
data bus
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