參數(shù)資料
型號: LPC2926FBD144
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: ARM9 microcontroller with CAN, LIN, and USB
中文描述: 32-BIT, FLASH, 125 MHz, RISC MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT486-1, LQFP-144
文件頁數(shù): 42/95頁
文件大?。?/td> 1855K
代理商: LPC2926FBD144
LPC2926_27_29
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 5 — 28 September 2010
42 of 95
NXP Semiconductors
LPC2926/2927/2929
ARM9 microcontroller with CAN, LIN, and USB
6.15.4.1
Functional description
The ADC block diagram,
Figure 9
, shows the basic architecture of each ADC. The ADC
functionality is divided into two major parts; one part running on the MSCSS Subsystem
clock, the other on the ADC clock. This split into two clock domains affects the behavior
from a system-level perspective. The actual analog-to-digital conversions take place in the
ADC clock domain, but system control takes place in the system clock domain.
A mechanism is provided to modify configuration of the ADC and control the moment at
which the updated configuration is transferred to the ADC domain.
The ADC clock is limited to 4.5 MHz maximum frequency and should always be lower
than or equal to the system clock frequency. To meet this constraint or to select the
desired lower sampling frequency, the clock generation unit provides a programmable
fractional system-clock divider dedicated to the ADC clock. Conversion rate is determined
by the ADC clock frequency divided by the number of resolution bits plus one. Accessing
ADC registers requires an enabled ADC clock, which is controllable via the clock
generation unit, see
Section 6.16.2
.
Each ADC has four start inputs. Note that start 0 and start 2 are captured in the system
clock domain while start 1 and start 3 are captured in the ADC domain. The start inputs
are connected at MSCSS level, see
Section 6.15
for details.
6.15.4.2
Pin description
The three ADC modules in the MSCSS have the pins described below. The ADCx input
pins are combined with other functions on the port pins of the LPC2926/2927/2929. The
VREFN and VREFP pins are common to all ADCs.
Table 23
shows the ADC pins.
Fig 9.
ADC block diagram
002aae360
start 2
start 0
system clock
ADC clock
(up to 4.5 MHz)
APB system bus
IRQ scan
IRQ compare
ADC1 IN[7:0]
ADC2 IN[7:0]
start 1
start 3
sync_out
ADC DOMAIN
SYSTEM DOMAIN
ADC
CONTROL
AND
REGISTERS
ADC
CONTROL
AND
REGISTERS
3.3 V
ADC1/2
ANALOG
MUX
conversion data
update
configuration data
IRQ
ADC0 IN[7:0]
5 V
ADC0
3.3 V
ANALOG
MUX
5 V IN
3.3 V IN
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