參數(shù)資料
型號: LPC2926FBD144
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: ARM9 microcontroller with CAN, LIN, and USB
中文描述: 32-BIT, FLASH, 125 MHz, RISC MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT486-1, LQFP-144
文件頁數(shù): 30/95頁
文件大小: 1855K
代理商: LPC2926FBD144
LPC2926_27_29
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 5 — 28 September 2010
30 of 95
NXP Semiconductors
LPC2926/2927/2929
ARM9 microcontroller with CAN, LIN, and USB
6.12.4.1
Pin description
The event router module in the LPC2926/2927/2929 is connected to the pins listed below.
The pins are combined with other functions on the port pins of the LPC2926/2927/2929.
Table 15
shows the pins connected to the event router.
Table 15.
Symbol
EXTINT[0:7]
CAN0 RXD
CAN1 RXD
I2C0_SCL
I2C1_SCL
LIN0 RXD
LIN1 RXD
SPI0 SDI
SPI1 SDI
SPI2 SDI
UART0 RXD
UART1 RXD
USB_SCL
-
-
-
6.13 Peripheral subsystem
6.13.1
Peripheral subsystem clock description
The peripheral subsystem is clocked by a number of different clocks:
CLK_SYS_PESS
CLK_UART0/1
CLK_SPI0/1/2
CLK_TMR0/1/2/3
CLK_SAFE see
Section 6.7.2
6.13.2
Watchdog timer
The purpose of the watchdog timer is to reset the ARM9 processor within a reasonable
amount of time if the processor enters an error state. The watchdog generates a system
reset if the user program fails to trigger it correctly within a predetermined amount of time.
Key features:
Internal chip reset if not periodically triggered
Timer counter register runs on always-on safe clock
Optional interrupt generation on watchdog time-out
Event-router pin connections
Direction
I
I
I
I
I
I
I
I
I
I
I
I
I
n/a
n/a
n/a
Description
external interrupt input 0 to 7
CAN0 receive data input wake-up
CAN1 receive data input wake-up
I2C0 SCL clock input
I2C1 SCL clock input
LIN0 receive data input wake-up
LIN1 receive data input wake-up
SPI0 receive data input
SPI1 receive data input
SPI2 receive data input
UART0 receive data input
UART1 receive data input
USB I
2
C-bus serial clock
CAN interrupt (internal)
VIC FIQ (internal)
VIC IRQ (internal)
Default polarity
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
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