參數(shù)資料
型號(hào)： LPC2925FBD100
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： ARM9 microcontroller with CAN, LIN, and USB
中文描述： 32-BIT, FLASH, 125 MHz, RISC MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT407-1, LQFP-100
文件頁數(shù)： 64/84頁
文件大?。?/td> 551K
代理商： LPC2925FBD100
LPC2921_23_25_3
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 14 April 2010
64 of 84
NXP Semiconductors
LPC2921/2923/2925
ARM9 microcontroller with CAN, LIN, and USB
9. Dynamic characteristics
9.1 Dynamic characteristics: I/O and CLK_OUT pins, internal clock,
oscillators, PLL, and CAN
[1]
All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at T
amb
= 85
°
C ambient
temperature on wafer level. Cased products are tested at T
amb
= 25
°
C (final testing). Both pre-testing and final testing use correlated
test conditions to cover the specified temperature and power supply voltage range.
[2]
See
Table 24
.
[3]
This parameter is not part of production testing or final testing, hence only a typical value is stated.
[4]
Oscillator start-up time depends on the quality of the crystal. For most crystals it takes about 1000 clock pulses until the clock is fully
stable.
Table 33.
V
DD(CORE)
= V
DD(OSC_PLL)
; V
DD(IO)
= 2.7 V to 3.6 V; V
DDA(ADC3V3)
= 3.0 V to 3.6 V; all voltages are measured with respect to
ground; positive currents flow into the IC; unless otherwise specified.
[1]
Symbol
Parameter
Conditions
I/O pins
t
THL
HIGH to LOW
transition time
t
TLH
LOW to HIGH
transition time
CLK_OUT pin
f
clk
clock frequency
on pin CLK_OUT
Internal clock
f
clk(sys)
system clock
frequency
T
clk(sys)
system clock period
Low-power ring oscillator
f
ref(RO)
RO reference
frequency
t
startup
start-up time
at maximum frequency
Oscillator
f
i(osc)
oscillator input
frequency
clock input of an external
clock source applied to the
XIN_OSC pin
t
startup
start-up time
at maximum frequency
Dynamic characteristics
Min
Typ
Max
Unit
C
L
= 30 pF
4
-
13.8
ns
C
L
= 30 pF
4
-
13.8
ns
-
-
40
MHz
[2]
10
-
125
MHz
[2]
8
-
100
ns
0.4
0.5
0.6
MHz
[3]
-
6
-
μ
s
maximum frequency is the
10
-
100
MHz
[3]
[4]
-
500
-
μ
s
PLL
f
i(PLL)
f
o(PLL)
PLL input frequency
PLL output frequency
10
10
156
-
-
-
-
-
-
-
25
160
320
63.4
60.3
MHz
MHz
MHz
ns
ns
CCO; direct mode
t
a(clk)
t
a(A)
Jitter specification for CAN
t
jit(cc)(p-p)
clock access time
address access time
cycle to cycle jitter
(peak-to-peak value)
on CAN TXDC pin
[3]
-
0.4
1
ns
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