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參數(shù)資料
| 型號： | LPC2925FBD100 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | ARM9 microcontroller with CAN, LIN, and USB |
| 中文描述： | 32-BIT, FLASH, 125 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT407-1, LQFP-100 |
| 文件頁數(shù)： | 24/84頁 |
| 文件大?。?/td> | 551K |
| 代理商： | LPC2925FBD100 |
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LPC2921_23_25_3
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 14 April 2010
24 of 84
NXP Semiconductors
LPC2921/2923/2925
ARM9 microcontroller with CAN, LIN, and USB
Watchdog control register change-protected with key
Programmable 32-bit watchdog timer period with programmable 32-bit prescaler.
6.12.2.1
Functional description
The watchdog timer consists of a 32-bit counter with a 32-bit prescaler.
The watchdog should be programmed with a time-out value and then periodically
restarted. When the watchdog times out, it generates a reset through the RGU.
To generate watchdog interrupts in watchdog debug mode the interrupt has to be enabled
via the interrupt enable register. A watchdog-overflow interrupt can be cleared by writing
to the clear-interrupt register.
Another way to prevent resets during debug mode is via the Pause feature of the
watchdog timer. The watchdog is stalled when the ARM9 is in debug mode and the
PAUSE_ENABLE bit in the watchdog timer control register is set.
The Watchdog Reset output is fed to the Reset Generator Unit (RGU). The RGU contains
a reset source register to identify the reset source when the device has gone through a
reset. See
Section 6.15.4
.
6.12.2.2
Clock description
The watchdog timer is clocked by two different clocks; CLK_SYS_PESS and CLK_SAFE,
see
Section 6.7.2
. The register interface towards the system bus is clocked by
CLK_SYS_PESS. The timer and prescale counters are clocked by CLK_SAFE which is
always on.
6.12.3
Timer
The LPC2921/2923/2925 contains six identical timers: four in the peripheral subsystem
and two in the Modulation and Sampling Control SubSystem (MSCSS) located at different
peripheral base addresses. This section describes the four timers in the peripheral
subsystem. Each timer has four capture inputs and/or match outputs. Connection to
device pins depends on the configuration programmed into the port function-select
registers. The two timers located in the MSCSS have no external capture or match pins,
but the memory map is identical, see
Section 6.14.6
. One of these timers has an external
input for a pause function.
The key features are:
32-bit timer/counter with programmable 32-bit prescaler.
Up to four 32-bit capture channels per timer. These take a snapshot of the timer value
when an external signal connected to the TIMERx CAPn input changes state. A
capture event may also optionally generate an interrupt.
Four 32-bit match registers per timer that allow:
–
Continuous operation with optional interrupt generation on match.
–
Stop timer on match with optional interrupt generation.
–
Reset timer on match with optional interrupt generation.
Up to four external outputs per timer corresponding to match registers, with the
following capabilities:
–
Set LOW on match.
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| LPC2925FBD100,551 | 功能描述:ARM微控制器 - MCU IC ARM9 MCU FLASH 512KB RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
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