參數(shù)資料
型號(hào): LPC2925FBD100
廠商: NXP SEMICONDUCTORS
元件分類(lèi): 微控制器/微處理器
英文描述: ARM9 microcontroller with CAN, LIN, and USB
中文描述: 32-BIT, FLASH, 125 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT407-1, LQFP-100
文件頁(yè)數(shù): 41/84頁(yè)
文件大?。?/td> 551K
代理商: LPC2925FBD100
LPC2921_23_25_3
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 14 April 2010
41 of 84
NXP Semiconductors
LPC2921/2923/2925
ARM9 microcontroller with CAN, LIN, and USB
6.15.1
Clock description
The PCRSS is clocked by a number of different clocks. CLK_SYS_PCRSS clocks the
AHB side of the AHB to DTL bus bridge and CLK_PCR_SLOW clocks the CGU, RGU and
PMU internal logic, see
Section 6.7.2
. CLK_SYS_PCRSS is derived from
BASE_SYS_CLK, which can be switched off in low-power modes. CLK_PCR_SLOW is
derived from BASE_PCR_CLK and is always on in order to be able to wake up from
low-power modes.
Fig 8.
Power, Clock, and Reset control SubSystem (PCRSS) block diagram
002aae249
AHB2DTL
BRIDGE
RESET OUTPUT
DELAY LOGIC
INPUT
DEGLITCH/
SYNC
branch
clocks
grant
request
wakeup_a
AHB_RST
SCU_RST
WARM_RST
COLD_RST
PCR_RST
RGU_RST
POR_RST
RST (device pin)
reset from watchdog counter
EXTERNAL
OSCILLATOR
PMU
REGISTERS
CLOCK
ENABLE
CONTROL
CLOCK
GATES
LOW POWER
RING
OSCILLATOR
CGU0
REGISTERS
RGU
REGISTERS
POR
OUT0
OUT1
OUT5
OUT7
OUT9
OUT6
OUT11
OUT0
OUT2
PLL
FDIV[6:0]
PLL
FDIV
CGU0
CGU1
PMU
RGU
AHB
master
disable:
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