參數(shù)資料
型號: LPC2925FBD100
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: ARM9 microcontroller with CAN, LIN, and USB
中文描述: 32-BIT, FLASH, 125 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT407-1, LQFP-100
文件頁數(shù): 25/84頁
文件大小: 551K
代理商: LPC2925FBD100
LPC2921_23_25_3
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 14 April 2010
25 of 84
NXP Semiconductors
LPC2921/2923/2925
ARM9 microcontroller with CAN, LIN, and USB
Set HIGH on match.
Toggle on match.
Do nothing on match.
Pause input pin (MSCSS timers only).
The timers are designed to count cycles of the clock and optionally generate interrupts or
perform other actions at specified timer values, based on four match registers. They also
include capture inputs to trap the timer value when an input signal changes state,
optionally generating an interrupt. The core function of the timers consists of a 32 bit
prescale counter triggering the 32 bit timer counter. Both counters run on clock
CLK_TMRx (x runs from 0 to 3) and all time references are related to the period of this
clock. Note that each timer has its individual clock source within the Peripheral
SubSystem. In the Modulation and Sampling SubSystem each timer also has its own
individual clock source. See
Section 6.15.5
for information on generation of these clocks.
6.12.3.1
Pin description
The four timers in the peripheral subsystem of the LPC2921/2923/2925 have the pins
described below. The two timers in the modulation and sampling subsystem have no
external pins except for the pause pin on MSCSS timer 1. See
Section 6.14.6
for a
description of these timers and their associated pins. The timer pins are combined with
other functions on the port pins of the LPC2921/2923/2925, see
Section 6.11.3
. Table
Table 13
shows the timer pins (x runs from 0 to 3).
Table 13.
Symbol
TIMERx CAP[0]
TIMERx CAP[1]
TIMERx CAP[2]
TIMERx CAP[3]
TIMERx MAT[0]
TIMERx MAT[1]
TIMERx MAT[2]
TIMERx MAT[3]
[1]
Note that CAP1[0] and CAP1[1] are not pinned out on Timer1.
6.12.3.2
Clock description
The timer modules are clocked by two different clocks; CLK_SYS_PESS and CLK_TMRx
(x = 0 to 3), see
Section 6.7.2
. Note that each timer has its own CLK_TMRx branch clock
for power management. The frequency of all these clocks is identical as they are derived
from the same base clock BASE_CLK_TMR. The register interface towards the system
bus is clocked by CLK_SYS_PESS. The timer and prescale counters are clocked by
CLK_TMRx.
6.12.4
UARTs
The LPC2921/2923/2925 contains two identical UARTs located at different peripheral
base addresses. The key features are:
16-byte receive and transmit FIFOs.
Timer pins
Pin name
CAPx[0]
CAPx[1]
CAPx[2]
CAPx[3]
MATx[0]
MATx[1]
MATx[2]
MATx[3]
Direction
IN
IN
IN
IN
OUT
OUT
OUT
OUT
Description
TIMERx capture input 0
[1]
TIMERx capture input 1
[1]
TIMERx capture input 2
TIMERx capture input 3
TIMERx match output 0
TIMERx match output 1
TIMERx match output 2
TIMERx match output 3
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