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| 型號： | LPC2925FBD100 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | ARM9 microcontroller with CAN, LIN, and USB |
| 中文描述： | 32-BIT, FLASH, 125 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT407-1, LQFP-100 |
| 文件頁數(shù)： | 38/84頁 |
| 文件大?。?/td> | 551K |
| 代理商： | LPC2925FBD100 |
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LPC2921_23_25_3
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 14 April 2010
38 of 84
NXP Semiconductors
LPC2921/2923/2925
ARM9 microcontroller with CAN, LIN, and USB
6.14.5.3
Master and slave mode
A PWM module can provide synchronization signals to other modules (also called Master
mode). The signal sync_out is a pulse of one clock cycle generated when the internal
PWM counter (re)starts. The signal trans_enable_out is a pulse synchronous to sync_out,
generated if a transfer from system registers to PWM shadow registers occurred when the
PWM counter restarted. A delay may be inserted between the counter start and
generation of trans_enable_out and sync_out.
A PWM module can use input signals trans_enable_in and sync_in to synchronize its
internal PWM counter and the transfer of shadow registers (Slave mode).
6.14.5.4
Pin description
Each of the four PWM modules in the MSCSS has the following pins. These are combined
with other functions on the port pins of the LPC2921/2923/2925.
Table 21
shows the
PWM0 to PWM3 pins (n = 0 to 3).
Table 21.
Symbol
PWMn CAP[0]
PWMn CAP[1]
PWMn CAP[2]
PWMn MAT[0]
PWMn MAT[1]
6.14.5.5
Clock description
The PWM modules are clocked by CLK_MSCSS_PWMx (x = 0 to 3), see
Section 6.7.2
.
Note that each PWM has its own CLK_MSCSS_PWMx branch clock for power
management. The frequency of all these clocks is identical to CLK_MSCSS_APB since
they are derived from the same base clock BASE_MSCSS_CLK.
Also note that unlike the timer modules in the Peripheral SubSystem, the actual timer
counter registers of the PWM modules run at the same clock as the APB system interface
CLK_MSCSS_APB. This clock is independent of the AHB system clock.
If a PWM module is not used its CLK_MSCSS_PWMx branch clock can be switched off.
6.14.6
Timers in the MSCSS
The two timers in the MSCSS are functionally identical to the timers in the peripheral
subsystem, see
Section 6.12.3
. The features of the timers in the MSCSS are the same as
the timers in the peripheral subsystem, but the capture inputs and match outputs are not
available on the device pins. These signals are instead connected to the ADC and PWM
modules as outlined in the description of the MSCSS, see
Section 6.14.1
.
See
Section 6.12.3
for a functional description of the timers.
PWM pins
Pin name
PCAPn[0]
PCAPn[1]
PCAPn[2]
PMATn[0]
PMATn[1]
Direction
IN
IN
IN
OUT
OUT
Description
PWMn capture input 0
PWMn capture input 1
PWMn capture input 2
PWMn match output 0
PWMn match output 1
PWMn MAT[2]
PWMn MAT[3]
PWMn MAT[4]
PWMn MAT[5]
PWMn TRAP
PMATn[2]
PMATn[3]
PMATn[4]
PMATn[5]
TRAPn
OUT
OUT
OUT
OUT
IN
PWMn match output 2
PWMn match output 3
PWMn match output 4
PWMn match output 5
PWMn trap input (on the LPC2921/2923/2925
n = 2, 3)
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