參數(shù)資料
型號： LPC2925FBD100
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： ARM9 microcontroller with CAN, LIN, and USB
中文描述： 32-BIT, FLASH, 125 MHz, RISC MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT407-1, LQFP-100
文件頁數(shù)： 46/84頁
文件大小： 551K
代理商： LPC2925FBD100
LPC2921_23_25_3
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 14 April 2010
46 of 84
NXP Semiconductors
LPC2921/2923/2925
ARM9 microcontroller with CAN, LIN, and USB
Triple output phases:
For applications that require multiple clock phases two additional
clock outputs can be enabled by setting register P23EN to logic 1, thus giving three clocks
with a 120
°
phase difference. In this mode all three clocks generated by the analog
section are sent to the output dividers. When the PLL has not yet achieved lock the
second and third phase output dividers run unsynchronized, which means that the phase
relation of the output clocks is unknown. When the PLL LOCK register is set the second
and third phase of the output dividers are synchronized to the main output clock CLKOUT
PLL, thus giving three clocks with a 120
°
phase difference.
Direct output mode:
In normal operating mode (with DIRECT set to logic 0) the CCO
clock is divided by 2, 4, 8 or 16 depending on the value on the PSEL[1:0] input, giving an
output clock with a 50 % duty cycle. If a higher output frequency is needed the CCO clock
can be sent directly to the output by setting DIRECT to logic 1. Since the CCO does not
directly generate a 50 % duty cycle clock, the output clock duty cycle in this mode can
deviate from 50 %.
Power-down control:
A Power-down mode has been incorporated to reduce power
consumption when the PLL clock is not needed. This is enabled by setting the PD control
register bit. In this mode the analog section of the PLL is turned off, the oscillator and the
phase-frequency detector are stopped and the dividers enter a reset state. While in
Power-down mode the LOCK output is low, indicating that the PLL is not in lock. When
Power-down mode is terminated by clearing the PD control-register bit the PLL resumes
normal operation, and makes the LOCK signal high once it has regained lock on the input
clock.
6.15.2.3
Pin description
The CGU0 module in the LPC2921/2923/2925 has the pins listed in
Table 25
below.
Table 25.
Symbol
XOUT_OSC
XIN_OSC
Fig 11. PLL block diagram
CCO
/ 2PDIV
P23
/ MDIV
002aad833
bypass
direct
clkout120
clkout240
clkout
clkout
input clock
PSEL bits
P23EN bit
MSEL bits
CGU0 pins
Direction
OUT
IN
Description
Oscillator crystal output
Oscillator crystal input or external clock input
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參數(shù)描述
LPC2925FBD100,551 功能描述:ARM微控制器 - MCU IC ARM9 MCU FLASH 512KB RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風格:SMD/SMT
LPC2926 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:ARM9 microcontroller with CAN, LIN, and USB
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LPC2926FBD144,557 制造商:NXP Semiconductors 功能描述:LPC2926FBD144/LQFP144/TRAYDPM/ - Trays 制造商:NXP Semiconductors 功能描述:IC MCU ARM9 256KB FLASH 144LQFP
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