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參數(shù)資料
| 型號： | LAN8700 |
| 廠商： | SMSC Corporation |
| 英文描述： | 【15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR TM in a Small Footprint |
| 中文描述： | 【15kV的ESD保護信息產(chǎn)業(yè)部/ RMII快速的HP Auto - MDIX功能和SMSC flexPWR商標(biāo)以太網(wǎng)PHY在小尺寸 |
| 文件頁數(shù)： | 50/73頁 |
| 文件大?。?/td> | 457K |
| 代理商： | LAN8700 |
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±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR
TM
in a Small Footprint
Datasheet
Revision 1.0 (02-09-07)
50
SMSC LAN8700/LAN8700I
DATASHEET
5.4.3
Isolate Mode
The PHY data paths may be electrically isolated from the MII by setting register 0, bit 10 to a logic
one. In isolation mode, the PHY does not respond to the TXD, TX_EN and TX_ER inputs. The PHY
still responds to management transactions.
Isolation provides a means for multiple PHYs to be connected to the same MII without contention
occurring. The PHY is not isolated on power-up (bit 0:10 = 0).
5.4.4
Link Integrity Test
The LAN8700/LAN8700I performs the link integrity test as outlined in the IEEE 802.3u (Clause 24-15)
Link Monitor state diagram. The link status is multiplexed with the 10Mbps link status to form the
reportable link status bit in Serial Management Register 1, and is driven to the LINK LED.
The DSP indicates a valid MLT-3 waveform present on the RXP and RXN signals as defined by the
ANSI X3.263 TP-PMD standard, to the Link Monitor state-machine, using internal signal called
DATA_VALID. When DATA_VALID is asserted the control logic moves into a Link-Ready state, and
waits for an enable from the Auto Negotiation block. When received, the Link-Up state is entered, and
the Transmit and Receive logic blocks become active. Should Auto Negotiation be disabled, the link
integrity logic moves immediately to the Link-Up state, when the DATA_VALID is asserted.
Note that to allow the line to stabilize, the link integrity logic will wait a minimum of 330
μ
sec from the
time DATA_VALID is asserted until the Link-Ready state is entered. Should the DATA_VALID input be
negated at any time, this logic will immediately negate the Link signal and enter the Link-Down state.
When the 10/100 digital block is in 10Base-T mode, the link status is from the 10Base-T receiver logic.
5.4.5
Power-Down modes
There are 2 power-down modes for the Phy:
5.4.5.1
General Power-Down
This power-down is controlled by register 0, bit 11. In this mode the entire PHY, except the
management interface, is powered-down and stays in that condition as long as bit 0.11 is HIGH. When
bit 0.11 is cleared, the PHY powers up and is automatically reset.
5.4.5.2
Energy Detect Power-Down
This power-down mode is activated by setting bit 17.13 to 1. In this mode when no energy is present
on the line the PHY is powered down, except for the management interface, the SQUELCH circuit and
the ENERGYON logic. The ENERGYON logic is used to detect the presence of valid energy from
100Base-TX, 10Base-T, or Auto-negotiation signals
In this mode, when the ENERGYON signal is low, the PHY is powered-down, and nothing is
transmitted. When energy is received - link pulses or packets - the ENERGYON signal goes high, and
the PHY powers-up. It automatically resets itself into the state it had prior to power-down, and asserts
the nINT interrupt if the ENERGYON interrupt is enabled. The first and possibly the second packet
to activate ENERGYON may be lost.
When 17.13 is low, energy detect power-down is disabled.
5.4.6
Reset
The PHY has 3 reset sources:
Hardware reset (HWRST)
: connected to the nRST input, and to the internal POR signal.
If the nRST input is driven by an external source, it should be held LOW for at least
100 us to ensure
that the Phy is properly reset.
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