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參數(shù)資料
| 型號： | LAN8700 |
| 廠商： | SMSC Corporation |
| 英文描述： | 【15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR TM in a Small Footprint |
| 中文描述： | 【15kV的ESD保護信息產業(yè)部/ RMII快速的HP Auto - MDIX功能和SMSC flexPWR商標以太網PHY在小尺寸 |
| 文件頁數(shù)： | 32/73頁 |
| 文件大?。?/td> | 457K |
| 代理商： | LAN8700 |
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±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR
TM
in a Small Footprint
Datasheet
Revision 1.0 (02-09-07)
32
SMSC LAN8700/LAN8700I
DATASHEET
.
4.12.2
I/O Voltage Stability
The I/O voltage the System Designer applies on VDDIO needs to maintain its value with a tolerance
of ± 10%. Varying the voltage up or down, after the PHY has completed power-on reset can cause
errors in the PHY operation.
4.13
PHY Management Control
The Management Control module includes 3 blocks:
Serial Management Interface (SMI)
Management Registers Set
Interrupt
4.13.1
Serial Management Interface (SMI)
The Serial Management Interface is used to control the LAN8700/LAN8700I and obtain its status. This
interface supports registers 0 through 6 as required by Clause 22 of the 802.3 standard, as well as
“vendor-specific” registers 16 to 31 allowed by the specification. Non-supported registers (7 to 15) will
be read as hexadecimal “FFFF”.
At the system level there are 2 signals, MDIO and MDC where MDIO is bi-directional open-drain and
MDC is the clock.
A special feature (enabled by register 17 bit 3) forces the PHY to disregard the PHY-Address in the
SMI packet causing the PHY to respond to any address. This feature is useful in multi-PHY
applications and in production testing, where the same register can be written in all the PHYs using a
single write transaction.
The MDC signal is an aperiodic clock provided by the station management controller (SMC). The MDIO
signal receives serial data (commands) from the controller SMC, and sends serial data (status) to the
SMC. The minimum time between edges of the MDC is 160 ns. There is no maximum time between
edges.
The minimum cycle time (time between two consecutive rising or two consecutive falling edges) is 400
ns. These modest timing requirements allow this interface to be easily driven by the I/O port of a
microcontroller.
The data on the MDIO line is latched on the rising edge of the MDC. The frame structure and timing
of the data is shown in
Figure 4.6
and
Figure 4.7
.
The timing relationships of the MDIO signals are further described in
Section 6.1, "Serial Management
Interface (SMI) Timing," on page 53
.
Table 4.3 Boot Strapping Configuration Resistors
I/O voltage
Pull-up/Pull-down Resistor
3.0 to 3.6
10k ohm resistor
2.0 to 3.0
7.5k ohm resistor
1.6 to 2.0
5k ohm resistor
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相關代理商/技術參數(shù) |
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| LAN8700AEZG | 制造商:SMSC 功能描述: |
| LAN8700-AEZG | 功能描述:以太網 IC HIPERFRM ETHRNT PHY RoHS:否 制造商:Micrel 產品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| LAN8700C-AEZG | 功能描述:以太網 IC IC w/HP Auto-MDIX Embedded Ethernet RoHS:否 制造商:Micrel 產品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| LAN8700C-AEZG-AR2 | 制造商:Microchip Technology Inc 功能描述: 制造商:Microchip Technology Inc 功能描述:MII/RMII 10/100 ETHERNET TRANSCEIVER - Trays 制造商:Microchip Technology Inc 功能描述:TXRX ETHERNET 10/100 36-VQFN 制造商:Microchip Technology Inc 功能描述:Ethernet ICs MII/RMII 10/100 制造商:Microchip Technology Inc 功能描述:MII/RMII 10/100 Ethernet Transceiver, 36 VQFN 6x6x0.9 TRAY |
| LAN8700C-AEZG-TR | 功能描述:以太網 IC Hi Perform Ethernet PHY RoHS:否 制造商:Micrel 產品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
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