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參數(shù)資料

型號：	LAN8700
廠商：	SMSC Corporation
英文描述：	【15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR TM in a Small Footprint
中文描述：	【15kV的ESD保護(hù)信息產(chǎn)業(yè)部/ RMII快速的HP Auto - MDIX功能和SMSC flexPWR商標(biāo)以太網(wǎng)PHY在小尺寸
文件頁數(shù)：	20/73頁
文件大?。?/td>	457K
代理商：	LAN8700

±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR

in a Small Footprint

Datasheet

Revision 1.0 (02-09-07)

SMSC LAN8700/LAN8700I

DATASHEET

4.2.3

Scrambling

Repeated data patterns (especially the IDLE code-group) can have power spectral densities with large

narrow-band peaks. Scrambling the data helps eliminate these peaks and spread the signal power

more uniformly over the entire channel bandwidth. This uniform spectral density is required by FCC

regulations to prevent excessive EMI from being radiated by the physical wiring.

The seed for the scrambler is generated from the PHY address, PHYAD[4:0], ensuring that in multiple-

PHY applications, such as repeaters or switches, each PHY will have its own scrambler sequence.

The scrambler also performs the Parallel In Serial Out conversion (PISO) of the data.

4.2.4

NRZI and MLT3 Encoding

The scrambler block passes the 5-bit wide parallel data to the NRZI converter where it becomes a

serial 125MHz NRZI data stream. The NRZI is encoded to MLT-3. MLT3 is a tri-level code where a

change in the logic level represents a code bit “1” and the logic output remaining at the same level

represents a code bit “0”.

4.2.5

100M Transmit Driver

The MLT3 data is then passed to the analog transmitter, which drives the differential MLT-3 signal, on

outputs TXP and TXN, to the twisted pair media across a 1:1 ratio isolation transformer. The 10Base-

T and 100Base-TX signals pass through the same transformer so that common “magnetics” can be

used for both. The transmitter drives into the 100

impedance of the CAT-5 cable. Cable termination

and impedance matching require external components.

4.2.6

100M Phase Lock Loop (PLL)

The 100M PLL locks onto reference clock and generates the 125MHz clock used to drive the 125 MHz

logic and the 100Base-Tx Transmitter.

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