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參數(shù)資料
| 型號： | L6566BTR |
| 廠商： | 意法半導體 |
| 英文描述： | Multi-mode controller for SMPS |
| 中文描述： | 多模式開關電源控制器 |
| 文件頁數(shù)： | 32/51頁 |
| 文件大?。?/td> | 401K |
| 代理商： | L6566BTR |
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Application information
L6566B
32/51
Equation 9
which is the parameter that the amplitude of the generated side-band harmonics depends
on.
The minimum frequency f
sw_min
(occurring on the peak of the triangle) and the maximum
frequency f
sw_max
(occurring on the valley of the triangle) will be symmetrically placed
around the centre value f
sw
, so that:
Equation 10
Then, R
T
will be found from (5) (see
Section 5.2: Zero current detection and triggering block;
oscillator block on page 21
), while R
MOD
and C
MOD
can be calculated as follows:
Equation 11
where
f
sw
and f
m
(in kHz, with C
MOD
in nF and R
MOD
in k
) will be selected by the user so
to achieve the best compromise between attenuation of peak EMI emissions and clean
converter operation.
5.9
Latched disable function
The device is equipped with a comparator having the non-inverting input externally available
at the pin DIS (8) and with the inverting input internally referenced to 4.5V. As the voltage on
the pin exceeds the internal threshold, the device is immediately shut down and its
consumption reduced to a low value.
The information is latched and it is necessary to let the voltage on the Vcc pin go below the
UVLO threshold to reset the latch and restart the device. To keep the latch supplied as long
as the converter is connected to the input source, the HV generator is activated periodically
so that Vcc oscillates between the start-up threshold V
ccON
and V
ccON
- 0.5V. Activating the
HV generator in this way cuts its power dissipation approximately by three (as compared to
the case of continuous conduction) and keeps peak silicon temperature close to the average
value.
To let the L6566B restart it is then necessary to disconnect the converter from the input
source. Pulling pin 16 (AC_OK) below the disable threshold (see
Section 5.12: Brownout
protection on page 37
) will stop the HV generator until Vcc falls below Vcc
restart
, so that the
latch can be cleared and a quicker restart is allowed as the input source is removed. This
operation is shown in the timing diagram of
Figure 20 on page 33
.
m
f
sw
f
=
β
sw
f
2
1
sw
f
max
_
sw
f
sw
f
2
1
sw
f
min
_
sw
f
;
+
=
=
sw
f
3
MOD
10
2
R
=
m
f
MOD
75
C
=
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