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參數(shù)資料
| 型號： | L6566BTR |
| 廠商： | 意法半導體 |
| 英文描述： | Multi-mode controller for SMPS |
| 中文描述： | 多模式開關(guān)電源控制器 |
| 文件頁數(shù)： | 25/51頁 |
| 文件大?。?/td> | 401K |
| 代理商： | L6566BTR |
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L6566B
Application information
25/51
Figure 12. Addition of an offset to the current sense lowers the burst-mode operation
threshold
Vcs
o
= Vref
5.4
Adaptive UVLO
A major problem when optimizing a converter for minimum no-load consumption is that the
voltage generated by the auxiliary winding under these conditions falls considerably as
compared even to a few mA load. This very often causes the supply voltage Vcc of the
control IC to drop and go below the UVLO threshold so that the operation becomes
intermittent, which is undesired. Furthermore, this must be traded off against the need of
generating a voltage not exceeding the maximum allowed by the control IC at full load.
To help the designer overcome this problem, the device, besides reducing its own
consumption during burst-mode operation, also features a proprietary adaptive UVLO
function. It consists of shifting the UVLO threshold downwards at light load, namely when
the voltage at pin COMP falls below a threshold V
COMPO
internally fixed, so as to have more
headroom. To prevent any malfunction during transients from minimum to maximum load
the normal (higher) UVLO threshold is re-established when the voltage at pin COMP
exceeds V
COMPL
and Vcc has exceeded the normal UVLO threshold (see
Figure 13
). The
normal UVLO threshold ensures that at full load the MOSFET will be driven with a proper
gate-to-source voltage.
Rs
L6566B
R
Vref
Rc
10
4
7
3
R
R + Rc
Figure 13. Adaptive UVLO block
V
COMPL
V
COMPO
VCOMP
(pin 9)
Vcc
(pin 5)
Q
OFF1
Vcc
OFF2
t
t
t
(*) Vcc
OFF2
< Vcc
OFF1
is selected when Q is high
+
-
UVLO
Vcc
OFF1
Vcc
L6566B
COMP
R
S Q
+
-
+
-
Vcc
OFF2
(*)
SW
5
9
V
COMPL
V
COMPO
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